IP Library › Granted Patent US 12,538,722
Granted Patent B2
US 12,538,722 · App. 18/665,023 · Granted Jan 27, 2026

Display device and method of fabricating the same

Inventors: Sang Sub Kim (Suwon-si, KR); Keun Woo Kim (Seongnam-si, KR); Ji Yeong Shin (Suwon-si, KR); Yong Su Lee (Seoul, KR); Myoung Geun Cha (Seoul, KR); Ki Seok Choi (Seoul, KR); Sang Gun Choi (Suwon-si, KR)
Assignee: Samsung Display Co., LTD.
H01L21/26533H10D30/0321H10D86/0223H10K59/1213H01L21/2253H01L21/28158H10D86/481H10D86/60H10K59/1201
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Quick Facts
Patent No.
US 12,538,722
App. No.
18/665,023
Granted
Jan 27, 2026
Kind
B2
Abstract

A display device and method of fabricating the same are provided. The display device includes a substrate and a thin-film transistor formed on the substrate. The thin-film transistor includes a lower gate conductive layer disposed on the substrate, and a lower gate insulating film disposed on the lower gate conductive layer The lower gate insulating film includes an upper surface and sidewalls. The thin-film transistor includes an active layer disposed on the upper surface of the lower gate insulating film, the active layer including sidewalls. At least one of the sidewalls of the lower gate insulating film and at least one of the sidewalls of the active layer are aligned with each other.

Claims (45)

1 . A method of fabricating a display device, the method comprising:

forming a crystalline silicon pattern on a substrate;

forming an upper gate insulating film on the crystalline silicon pattern; and

dividing the crystalline silicon pattern into a lower gate insulating film and an active layer disposed on the lower gate insulating film, the active layer including crystalline silicon, the dividing of the crystalline silicon pattern including:

forming the active layer above the lower gate insulating film to completely cover an upper surface of the lower gate insulating film; and

aligning at least one inclined sidewall of the active layer with at least one inclined sidewall of the lower gate insulating film,

wherein the inclined sidewall of the active layer and the inclined sidewall of the lower gate insulating film are inclined with respect to an upper surface of the substrate,

wherein the lower gate insulating film is disposed between the active layer and the substrate.

2 . The method of claim 1 , wherein the forming of the crystalline silicon pattern on the substrate includes:

forming an amorphous silicon layer on the substrate;

patterning the amorphous silicon layer to form an amorphous silicon pattern; and

crystallizing the amorphous silicon pattern to form the crystalline silicon pattern.

3 . The method of claim 1 , wherein the dividing of the crystalline silicon pattern includes:

implanting oxygen into a lower portion of the crystalline silicon pattern; and

dividing the lower portion of the crystalline silicon pattern from an upper portion of the crystalline silicon pattern by forming the lower portion of the crystalline silicon pattern as the lower gate insulating film through heat treatment, the upper portion of the crystalline silicon pattern being the active layer including the crystalline silicon.

4 . The method of claim 3 , further comprising, prior to the forming of the crystalline silicon pattern on the substrate:

forming a lower gate conductive layer on the substrate; and

forming a buffer layer on the lower gate conductive layer and the substrate, wherein

the lower gate conductive layer is disposed below the crystalline silicon pattern to overlap the crystalline silicon pattern, and

the buffer layer is disposed on an entire surface of the substrate and is disposed between the crystalline silicon pattern and the lower gate conductive layer.

5 . The method of claim 4 , wherein

the lower gate insulating film includes silicon oxide,

the buffer layer includes silicon oxide, and

an oxygen content of the lower gate insulating film is higher than an oxygen content of the buffer layer.

6 . A method of fabricating a display device, the method comprising:

forming a crystalline silicon pattern on a substrate;

forming an upper gate insulating film on the crystalline silicon pattern; and

dividing the crystalline silicon pattern into a lower gate insulating film and an active layer disposed on the lower gate insulating film, the active layer including crystalline silicon, the dividing of the crystalline silicon pattern including:

forming the active layer above the lower gate insulating film to completely cover an upper surface of the lower gate insulating film; and

aligning at least one of sidewalls of the active layer with at least one of sidewalls of the lower gate insulating film,

wherein the dividing of the crystalline silicon pattern includes:

implanting oxygen into a lower portion of the crystalline silicon pattern; and

dividing the lower portion of the crystalline silicon pattern from an upper portion of the crystalline silicon pattern by forming the lower portion of the crystalline silicon pattern as the lower gate insulating film through heat treatment, the upper portion of the crystalline silicon pattern being the active layer including the crystalline silicon.

7 . The method of claim 6 , further comprising, prior to the forming of the crystalline silicon pattern on the substrate:

forming a lower gate conductive layer on the substrate; and

forming a buffer layer on the lower gate conductive layer and the substrate, wherein the lower gate conductive layer is disposed below the crystalline silicon pattern to overlap the crystalline silicon pattern, and

the buffer layer is disposed on an entire surface of the substrate and is disposed between the crystalline silicon pattern and the lower gate conductive layer.

8 . The method of claim 7 , wherein

the lower gate insulating film includes silicon oxide,

the buffer layer includes silicon oxide, and

an oxygen content of the lower gate insulating film is higher than an oxygen content of the buffer layer.

9 . The method of claim 6 , wherein the forming of the crystalline silicon pattern on the substrate includes:

forming an amorphous silicon layer on the substrate;

patterning the amorphous silicon layer to form an amorphous silicon pattern; and

crystallizing the amorphous silicon pattern to form the crystalline silicon pattern.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2024
From: KIM, SANG SUB; KIM, KEUN WOO; SHIN, JI YEONG; LEE, YONG SU; CHA, MYOUNG GEUN; CHOI, KI SEOK; CHOI, SANG GUN
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 067424/0208 →
Priority Claims (1)
KR 10-2019-0149743 · Nov 20, 2019 · national
Continuity (3)
Division 18122815 · Mar 17, 2023
Division 17071579 · Oct 15, 2020
Related Publication 20240304726A1 · Sep 12, 2024
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