IP Library › Granted Patent US 11,437,346
Granted Patent B2
US 11,437,346 · App. 16/025,710 · Granted Sep 6, 2022

Package structure having substrate thermal vent structures for inductor cooling

Inventors: Michael J. Hill (Gilbert, AZ); Leigh E. Wojewoda (Tempe, AZ); Mathew Manusharow (Phoenix, AZ); Siddharth Kulasekaran (Tempe, AZ)
Assignee: Intel Corporation
H01L25/0652H01F27/085H01L23/34H01L23/645H01L28/10
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,437,346
App. No.
16/025,710
Granted
Sep 6, 2022
Kind
B2
Abstract

Embodiments include a microelectronic device package structure having an inductor within a portion of a substrate, wherein the inductor is at least partially embedded within the substrate. One or more thermal vent structures extend through at least one of the substrate or a board attached to the substrate. The one or more thermal vent structures provide a thermal pathway for cooling for the inductor.

Claims (32)

1. A method of fabricating a microelectronic package structure, comprising:

forming an inductor within a substrate, wherein the inductor is at least partially embedded within the substrate;

attaching a die on a surface of the substrate;

forming a substrate opening extending one or more openings vertically through the substrate, wherein the substrate opening is between a first portion of the substrate and a second portion of the substrate, wherein the inductor is within the first portion of the substrate and is within a footprint of the die;

attaching a board on the substrate; and

forming a board opening through the board, wherein the board openings is aligned with the substrate opening.

2. The method of fabricating the microelectronic package structure of claim 1 , wherein forming the inductor comprises forming a plurality of inductor layers within a recess of the substrate, wherein individual layers are coupled to each other by one or more via structures, and wherein a first side of the inductor is embedded within the substrate, and a portion of a second side of the inductor is substantially coplanar with a second side of the first portion of the substrate.

3. A microelectronic device package structure comprising:

a substrate comprising a first portion and a second portion;

a die comprising an integrated circuit, wherein the die is on a first side of the first portion of the substrate;

an inductor, wherein the inductor is at least partially embedded within the substrate; and

a substrate openings extending vertically through the substrate between the first portion and the second portion, wherein the substrate openings is adjacent a sidewall of the inductor, wherein a board comprises a board opening extending vertically through the board, wherein the board opening is aligned with the substrate opening.

4. The microelectronic device package structure of claim 3 , wherein a heat sink is on the die and is thermally coupled to the die, wherein the heat sink comprises an opening extending through the heat sink, and wherein the opening through the heat sink is over the substrate opening.

5. The microelectronic device package structure of claim 3 wherein an air funnel is adjacent the die and on the first side of the first portion of the substrate, and a fan is adjacent the air funnel.

6. The microelectronic device package structure of claim 3 , wherein the inductor comprises a portion of an air core inductor.

7. The microelectronic device package structure of claim 3 , further comprising a board electrically coupled to the second side of the substrate.

8. The microelectronic device package structure of claim 7 , wherein one or more interconnect structures are on a first side of the board, wherein the one or more interconnect structures are adjacent a sidewall of the board opening.

9. An assembly comprising:

a substrate, the substrate comprising a first side and a second side opposite the first side, wherein the substrate comprises a first portion and a second portion;

a die on the first side of the first portion of the substrate, the die comprising an integrated circuit;

an inductor, wherein the inductor is at least partially embedded within the first portion of the substrate, and is within a footprint of the die;

a board electrically coupled to the second side of the substrate; and

an opening between the first portion and the second portion of the substrate, wherein the opening extends vertically from the first side of the substrate to a first side of the board, and

wherein the openings is adjacent a sidewall of the inductor.

10. The assembly of claim 9 wherein the inductor comprises an air core inductor, wherein the air core inductor comprises one or more conductive layers coupled to each other by one or more conductive via structures.

11. The assembly of claim 9 , wherein a first side of the die is on the first side of the substrate, and wherein a heat sink is on a second side of the die, and wherein the heat sink has an opening adjacent the die.

12. The assembly of claim 9 , wherein the die includes a portion of a voltage regulator, and wherein the inductor is electrically coupled to the voltage regulator.

13. The assembly of claim 9 , wherein an air funnel is on the first side of the substrate, adjacent the die.

14. The assembly of claim 9 , wherein an array of solder balls surrounds the die on a first portion of a peripheral region of the second side of the substrate, and wherein a second portion of the peripheral region of the second side of the substrate is free of the solder balls.

15. The assembly of claim 14 , wherein the openings is between the array and the die.

16. The assembly of claim 9 , wherein one or more interconnect structures are on a second side of the second portion of the substrate, adjacent a sidewall of the openings.

17. The assembly of claim 16 , wherein a stand-off region is between the second side of the first portion of the substrate and a first side of the board, wherein a portion of the standoff region beneath the inductor is free of the one or more interconnect structures, and wherein a first side of the inductor is embedded within the substrate, and a second side of the inductor is substantially coplanar with the second side of the substrate.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE CONVEYING PARTY PREVIOUSLY RECORDED AT REEL: 046550 FRAME: 0155. ASSIGNOR(S) HEREBY CONFIRMS THE ASSSIGNMENT. Recorded Aug 30, 2018
From: HILL, MICHAEL J.; WOJEWODA, LEIGH E.; MANUSHAROW, MATHEW; KULASEKARAN, SIDDHARTH
To: INTEL CORPORATION
Reel/Frame 046988/0843 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2018
From: HILL, MICHAEL J.; WOJEWODA, LEIGH E.; MANUSHAROW, MATHEW; KULASEKARAN, SIDDARTH
To: INTEL CORPORATION
Reel/Frame 046550/0155 →
Continuity (1)
Related Publication 20200006287A1 · Jan 2, 2020
Cited By (1)
US 12,550,412