Integrated circuit package and method

1. A method comprising:

forming first electrical connectors and second electrical connectors on a first side of an interposer wafer;

bonding an integrated circuit die to the first side of the interposer wafer using the first electrical connectors;

attaching a stiffener structure to the first side of the interposer wafer adjacent the integrated circuit die, the stiffener structure covering the second electrical connectors in a plan- view, wherein the stiffener structure comprises a first portion and a second portion disconnected from the first portion, the first portion extending along the first side of the interposer wafer in a first direction from a first edge of the interposer wafer to a second edge of the interposer wafer, the second portion extending along the first side of the interposer wafer in a second direction different from the first direction;

encapsulating the integrated circuit die and the stiffener structure with a first encapsulant; and

singulating the interposer wafer and the stiffener structure to form a stacked structure.

2. The method of claim 1 , wherein the stiffener structure is a dummy structure.

3. The method of claim 2 , wherein the stiffener structure is attached to the first side of the interposer wafer by an adhesive.

4. The method of claim 3 , wherein the adhesive extends along sidewalls and top surfaces of the second connectors.

5. The method of claim 1 , further comprising:

forming a first redistribution structure over a carrier substrate;

attaching the stacked structure to the first redistribution structure; and

encapsulating the stacked structure with a second encapsulant.

6. The method of claim 5 , further comprising forming a second redistribution structure over the stacked structure and the second encapsulant, wherein the stacked structure is interposed between the first redistribution structure and the second redistribution structure.

7. The method of claim 6 , further comprising, before encapsulating the stacked structure with the second encapsulant, forming a through via on the first redistribution structure adjacent the stacked structure, wherein the through via electrically couples the first redistribution structure to the second redistribution structure.

8. A method comprising:

forming first electrical connectors on a first side of an interposer wafer, the interposer wafer comprising die regions and scribe line regions, each of the scribe line regions being interposed between adjacent ones of the die regions;

bonding an active side of an integrated circuit die to the first side of the interposer wafer in a first die region of the die regions using a first group of the first electrical connectors;

attaching a stiffener structure to the first side of the interposer wafer adjacent the integrated circuit die, the stiffener structure overlapping the first die region and a first scribe line region of the scribe line regions adjacent the first die region in a plan view, a second group of the first electrical connectors being interposed between the stiffener structure and the interposer wafer;

encapsulating the integrated circuit die and the stiffener structure with a first encapsulant, a back side of the integrated circuit die being level with a first side of the first encapsulant;

forming second electrical connectors on a second side of the interposer wafer, the second side of the interposer wafer being opposite to the first side of the interposer wafer;

singulating the first die region of the interposer wafer from other die regions of the interposer wafer to form a stacked structure; and

encapsulating the stacked structure with a second encapsulant, the second encapsulant extending along sidewalls of the stacked structure, the second encapsulant having a first surface and a second surface opposite the first surface, the first surface of the second encapsulant being level with exposed surfaces of the second electrical connectors.

9. The method of claim 8 , wherein the stiffener structure is a dummy structure.

10. The method of claim 8 , further comprising forming a first redistribution structure on the exposed surfaces of the second electrical connectors and the first side of the second encapsulant.

11. The method of claim 10 , further comprising forming a second redistribution structure on the back side of the integrated circuit die and the second side of the second encapsulant.

12. The method of claim 8 , wherein the stiffener structure comprises an opening, and wherein the stacked structure is disposed in the opening.

13. The method of claim 8 , further comprising bonding a surface device to the first side of the interposer wafer in the first die region, wherein the first encapsulant extends along sidewalls and a top surface of the surface device.

14. A method comprising:

forming a first electrical connector, a second electrical connector, and a third electrical connector on a first side of an interposer wafer;

bonding an integrated circuit die to the first side of the interposer wafer using the first electrical connector;

attaching a stiffener structure to the first side of the interposer wafer adjacent the integrated circuit die, wherein the second electrical connector is interposed between the stiffener structure and the interposer wafer;

bonding a surface device to the first side of the interposer wafer using the third electrical connector, wherein the surface device is interposed between the integrated circuit die and the stiffener structure;

encapsulating the integrated circuit die, the stiffener structure, and the surface device with a first encapsulant, wherein a first surface of the integrated circuit die is level with a first surface of the first encapsulant, and wherein the first surface of the integrated circuit die and the first surface of the first encapsulant face away from the interposer wafer; and

dicing the interposer wafer and the stiffener structure to form a stacked structure.

15. The method of claim 14 , wherein the stiffener structure is a dummy structure.

16. The method of claim 15 , wherein the stiffener structure is attached to the first side of the interposer wafer by an adhesive.

17. The method of claim 16 , wherein the second electrical connector is embedded in the adhesive.

18. The method of claim 14 , wherein the stiffener structure has a greater thermal conductivity than the first encapsulant.

19. The method of claim 14 , wherein the first surface of the integrated circuit die is level with a first surface of the stiffener structure, and wherein the first surface of the stiffener structure faces away from the interposer wafer.

20. The method of claim 14 , wherein the stiffener structure does not comprise active circuitry.