Semiconductor package and method for fabricating base for semiconductor package
The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure.
1. A semiconductor package, comprising:
a base comprising a recess;
a copper trace embedded in the recess such that a top surface of the copper trace is below a top surface of the base, wherein the top surface of the copper trace is exposed within the recess; and
a semiconductor device mounted on the copper trace via a conductive structure that is in direct contact with the top surface of the copper trace, wherein
at least a portion of the conductive structure at or above the top surface of the base has a width that is greater than a width of the copper trace.
2. The semiconductor package of claim 1 , wherein a bottom surface of the recess and at least one side wall of the recess are formed of a same insulative material.
3. The semiconductor package of claim 1 , wherein the base covers an entirety of a bottom surface of the copper trace underneath the conductive structure.
4. The semiconductor package of claim 1 , wherein the copper trace is elongated and carries a signal or a ground across at least a portion of the base.
5. The semiconductor package of claim 1 , wherein the conductive structure is in contact with a portion of the top surface of the base and with a side wall of the recess.
6. The semiconductor package of claim 1 , wherein the conductive structure comprises a conductive pillar structure comprising an under bump metallurgy (UBM) layer, a copper layer, a solder cap and a conductive buffer layer between the copper layer and the solder cap.
7. The semiconductor package of claim 6 , wherein the UBM layer contacts an exposed portion of a metal pad of the semiconductor device, and wherein the solder cap is in contact with at least a portion of the top surface of the base, at least one side wall of the recess and the top surface of the copper trace.
8. A semiconductor package, comprising:
a base comprising a top surface and a recess having an insulative bottom surface below the top surface;
a conductive trace embedded in the recess such that the conductive trace is in contact with the insulative bottom surface, wherein a top surface of the conductive trace is below the top surface of the base; and
a semiconductor device mounted on the conductive trace via a conductive structure, wherein at least a portion of the conductive structure at or above the top surface of the base has a width that is greater than a width of the conductive trace,
wherein the conductive trace is elongated and carries a signal or a ground across at least a portion of the base.
9. The semiconductor package of claim 8 , wherein the conductive structure is in contact with an entire width of the top surface of the conductive trace.
10. The semiconductor package of claim 8 , wherein the insulative bottom surface of the recess and at least one side wall of the recess are formed of a same insulative material.
11. The semiconductor package of claim 8 , wherein the semiconductor device comprises a body having a first surface, a metal pad on the first surface, and an insulation layer covering at least a portion of the first surface of the body and a portion of the metal pad, wherein an exposed portion of the metal pad is mounted on the conductive trace via the conductive structure.
12. The semiconductor package of claim 8 , and wherein the top surface of the conductive trace and a bottom surface of the conductive trace have a same width.
13. The semiconductor package of claim 12 , wherein the width of the top surface of the conductive trace and the bottom surface of the conductive trace is the same as a width of a bottom surface of the recess.
14. The semiconductor package of claim 8 , wherein the conductive trace is a single layer.
15. The semiconductor package of claim 14 , wherein the base covers an entirety of a bottom surface of the conductive trace underneath the conductive structure.
16. The semiconductor package of claim 8 , further comprising:
an underfill between the semiconductor device and the base.
17. The semiconductor package of claim 16 , wherein the underfill comprises capillary underfill (CUF), molded underfill (MUF), nonconductive paste (NCP), nonconductive film (NCF) or a combination thereof.
18. The semiconductor package of claim 8 , wherein the conductive structure comprises a conductive pillar structure comprising an under bump metallurgy (UBM) layer, a copper layer, a solder cap and a conductive buffer layer between the copper layer and the solder cap.
19. The semiconductor package of claim 18 , wherein the copper layer has a width that is greater than a width of the conductive trace.
20. The semiconductor package of claim 18 , wherein the UBM layer contacts an exposed portion of a metal pad of the semiconductor device, and wherein the solder cap is in contact with at least a portion of the top surface of the base, at least one side wall of the recess and the top surface of the conductive trace.