Semiconductor package including a bridge die
A semiconductor package includes an outer redistributed line (RDL) structure, a first semiconductor chip disposed on the outer RDL structure, a stack module stacked on the first semiconductor chip, and a bridge die stacked on the outer RDL structure. A portion of the stack module laterally protrudes from a side surface of the first semiconductor chip. The bridge die supports the protruding portion of the stack module. The stack module includes an inner RDL structure, a second semiconductor chip disposed on the inner RDL structure, a capacitor die disposed on the inner RDL structure, and an inner encapsulant. The capacitor die acts as a decoupling capacitor of the second semiconductor chip.
1. A semiconductor package comprising:
an outer redistributed line (RDL) structure;
a first semiconductor chip disposed on the outer RDL structure;
a stack module stacked on the first semiconductor chip, wherein a portion of the stack module laterally protrudes from a side surface of the first semiconductor chip in a plan view; and
a bridge die stacked on the outer RDL structure to support the protruding portion of the stack module, wherein the bridge die includes conductive through vias electrically connecting the stack module to the outer RDL structure,
wherein the stack module includes:
an inner RDL structure;
a second semiconductor chip disposed on the inner RDL structure, wherein the second semiconductor chip includes chip pads electrically connected to the inner RDL structure;
a capacitor die disposed on the inner RDL structure and spaced apart from the second semiconductor chip, wherein the capacitor die includes a capacitor electrically connected to the chip pads through the inner RDL structure; and
an inner encapsulant formed on the inner RDL structure to cover the second semiconductor chip and the capacitor die.
2. The semiconductor package of claim 1 , wherein the capacitor die overlaps with the first semiconductor die.
3. The semiconductor package of claim 1 , wherein the capacitor includes:
a first electrode plate formed on a body of the capacitor die;
a dielectric layer formed on the first electrode plate;
a second electrode plate formed on the dielectric layer; and
a first electrode and a second electrode connected to respective one of the first electrode plate and the second electrode plate.
4. The semiconductor package of claim 3 ,
wherein the capacitor die includes a body having a surface providing trenches; and
wherein the first and second electrode plates and the dielectric layer extends into the trenches.
5. The semiconductor package of claim 4 , wherein the body of the capacitor die is comprised of a silicon material.
6. The semiconductor package of claim 3 , wherein the inner RDL structure includes:
a first inner RDL pattern extending to connect the first electrode to a first chip pad of the chip pads, wherein the first chip pad is a power terminal for applying a power supply voltage to the second semiconductor chip; and
a second inner RDL pattern extending to connect the second electrode to a second chip pad of the chip pads, wherein the second chip pad is a ground terminal for applying a ground voltage to the second semiconductor chip.
7. The semiconductor package of claim 1 ,
wherein the second semiconductor chip includes a memory semiconductor chip storing data; and
wherein the first semiconductor chip includes a system-on-chip (SoC) that communicates with the second semiconductor chip to receive or output the data.
8. The semiconductor package of claim 1 , further comprising an adhesive layer provided between the stack module and the first semiconductor chip to attach the stack module to the first semiconductor chip.
9. The semiconductor package of claim 1 , wherein the conductive through vias are formed to vertically penetrate a body of the bridge die.
10. The semiconductor package of claim 1 , further comprising an outer encapsulant disposed on the outer RDL structure to cover the first semiconductor chip, the bridge die, and the stack module.