Semiconductor device structure having a multi-layer conductive feature and method making the same
The present disclosure provides a method of forming a semiconductor device structure. The method includes forming a trench in a dielectric layer on a semiconductor substrate; forming a bottom metal feature of a first metal in a lower portion of the trench by a selective deposition; depositing a barrier layer in an upper portion of the trench, the barrier layer directly contacting both a top surface of the bottom metal feature and sidewalls of the dielectric layer; and forming a top metal feature of a second metal on the barrier layer, filling in the upper portion of the trench, wherein the second metal is different from the first metal in composition.
1. A method of forming a semiconductor device structure, comprising:
forming a first dielectric layer on a semiconductor substrate and a second dielectric layer over and in direct contact with the first dielectric layer;
forming a trench to extend through the first dielectric layer and the second dielectric layer;
forming a bottom metal feature of a first metal in a lower portion of the trench by a selective deposition process, wherein the bottom metal feature directly contacts the first dielectric layer on a first interface and directly contacts the second dielectric layer on a second interface, wherein the first interface aligns with the second interface;
depositing a barrier layer in an upper portion of the trench, the barrier layer directly contacting both a top surface of the bottom metal feature and sidewalls of the second dielectric layer; and
forming a top metal feature of a second metal on the barrier layer, thereby filling the top metal feature in the upper portion of the trench, wherein the second metal is different from the first metal in composition.
2. The method of claim 1 , wherein
the forming of the bottom metal feature includes depositing the first metal to directly contact the first dielectric layer and the second dielectric layer; and
the forming of the top metal feature includes depositing the second metal on the barrier layer such that the top metal feature is separated from the first dielectric layer and the second dielectric layer by the barrier layer, and a bottom surface of the top metal feature is above a top surface of the bottom metal feature.
3. The method of claim 1 , wherein a bottom of the trench exposes a conductive feature prior to forming the bottom metal feature, wherein depositing a barrier layer includes depositing the barrier layer on the sidewalls of the second dielectric layer in the upper portion of the trench, wherein the barrier layer is free from the first dielectric layer and portions of the second dielectric layer within the lower portion of the trench.
4. The method of claim 1 , wherein
the forming of the bottom metal feature includes forming the bottom metal feature of ruthenium (Ru);
the depositing of the barrier layer includes depositing a tantalum nitride (TaN) film and a tantalum (Ta) film on the TaN film; and
the forming of the top metal feature includes forming the top metal feature of copper (Cu).
5. The method of claim 4 , wherein the forming of the bottom metal feature includes depositing Ru by performing a chemical vapor deposition (CVD) process using a Ru-containing precursor with a deposition temperature ranging between 100° C. and 200° C.
6. The method of claim 4 , wherein the forming of the top metal feature includes
forming a seed layer of Cu on the barrier layer by one of atomic layer deposition (ALD) and physical vapor deposition (PVD);
filling Cu on the seed layer in the upper portion of the trench by plating; and
performing a chemical-mechanical polishing (CMP) process.
7. A method of forming a semiconductor device structure, comprising:
receiving a semiconductor substrate having a field-effect transistor formed thereon and a conductive structure disposed over and electrically connected to the field-effect transistor;
depositing a first dielectric layer over a top surface of the conductive structure;
depositing a second dielectric layer over the first dielectric layer;
patterning the first dielectric layer and the second dielectric layer to form a trench such that the top surface of the conductive structure is exposed within the trench, wherein the trench includes a lower portion and an upper portion continuously extending from the lower portion;
forming a bottom metal feature of a first metal in the lower portion of the trench, wherein the sidewalls of the second dielectric layer are exposed within the upper portion of the trench;
depositing a barrier layer on the bottom metal feature to directly contact the sidewalls of the second dielectric layer exposed within the upper portion of the trench, wherein entire sidewalls of the barrier layer are in direct contact with the second dielectric layer but not the first dielectric layer; and
forming a top metal feature of a second metal on the barrier layer, thereby filling the upper portion of the trench with the second metal.
8. The method of claim 7 , wherein
the forming of the bottom metal feature includes depositing the first metal to directly contact a top surface of the conductive structure and the sidewalls of the first dielectric layer and the second dielectric layer within the lower portion of the trench; and
the forming of the top metal feature includes depositing the second metal on the barrier layer so that the second metal is separated from the second dielectric layer and the bottom metal feature by the barrier layer and a bottom surface of the top metal feature is above a top surface of the first dielectric layer.
9. The method of claim 7 , wherein the first metal includes ruthenium (Ru) and the bottom-up deposition process selectively deposits Ru on a conductive surface of the conductive structure.
10. The method of claim 9 , wherein the forming of the bottom metal feature includes depositing Ru by performing a chemical vapor deposition (CVD) process using a ruthenium-containing precursor with a deposition temperature ranging between 100° C. and 200° C.
11. The method of claim 7 , wherein
the first metal includes at least one of ruthenium (Ru) and cobalt (Co);
the second metal includes copper (Cu); and
the barrier layer includes at least one of cobalt (Co), and tantalum (Ta).
12. The method of claim 7 , wherein the conductive structure is electrically connected to a gate electrode of the field-effect transistor, and wherein the bottom metal feature directly contacts the conductive structure.
13. The method of claim 7 , further comprising forming a contact feature to electrically connect a source/drain feature of the field-effect transistor to the conductive structure.
14. A method of forming a semiconductor device structure, comprising:
receiving a semiconductor substrate having a field-effect transistor formed thereon, the field-effect transistor, a conductive feature disposed over and electrically connected to the field-effect transistor, and a dielectric layer disposed over a top surface of the conductive feature;
patterning the dielectric layer to form a trench such that the top surface of the conductive feature is exposed within the trench, wherein the trench includes a lower portion and an upper portion continuously extending from the lower portion;
forming a bottom metal feature of a first metal in the lower portion of the trench, the bottom metal feature directly contacting the dielectric layer within the lower portion of the trench on a first interface;
depositing a barrier layer on the bottom metal feature, wherein topmost sidewalls of the barrier layer directly contact sidewalls of the dielectric layer within the upper portion of the trench that are not covered by the bottom metal feature on a second interface, wherein the first interface aligns with the second interface; and
filling a second metal on the barrier layer, thereby forming a top metal feature in the upper portion of the trench.
15. The method of claim 14 , wherein the conductive feature is landing on and electrically connected to a gate electrode of the field-effect transistor, and wherein the forming of the top metal feature includes
depositing the second metal on the barrier layer so that the second metal is separated from the dielectric layer and the bottom metal feature by the barrier layer; and
performing a chemical mechanical polishing (CMP) process to the deposited second metal.
16. The method of claim 14 , wherein the first metal includes ruthenium (Ru) and the bottom-up deposition process selectively deposits Ru on a conductive surface of the conductive feature.
17. The method of claim 16 , wherein the forming of the bottom metal feature includes depositing Ru by performing a chemical vapor deposition (CVD) process using a ruthenium-containing precursor with a deposition temperature ranging between 100° C. and 200° C.
18. The method of claim 14 , wherein
the first metal includes at least one of ruthenium (Ru) and cobalt (Co);
the second metal includes copper (Cu); and
the barrier layer includes at least one of cobalt (Co) and tantalum (Ta).
19. The method of claim 18 , wherein the conductive feature includes
tungsten (W), cobalt (Co), copper (Cu), tantalum (Ta), and ruthenium (Ru), and wherein the top surface of the conductive feature spans a first width and a bottom surface of the conductive feature spans a second width that is less than the first width.
20. The method of claim 1 , further comprising:
receiving a transistor formed over the semiconductor substrate; and
forming a conductive feature over and electrically connected to a gate electrode of the transistor, wherein the first dielectric layer is formed over the conductive feature, and wherein the bottom metal feature is formed to directly contact a top surface of the conductive feature.