Interconnect structure having a multi-deck conductive feature and method of forming the same
The present disclosure provides a semiconductor device structure that includes: a fin active region extruded above a semiconductor substrate; a gate stack disposed on the fin active region, wherein the gate stack includes a gate dielectric layer and a gate electrode; source/drain (S/D) features formed on the fin active region and interposed by the gate stack; and a conductive feature electrically connected to one of the gate electrode and the S/D features. The conductive feature includes a bottom metal feature of a first metal; a top metal feature of a second metal over the bottom metal feature, wherein the second metal is different from the first metal in composition; a barrier layer surrounding both the top metal feature and the bottom metal feature; and a liner surrounding both the top metal feature and separating the top metal feature from the bottom metal feature and the barrier layer.
1 . A method of forming a semiconductor device structure, comprising:
forming a trench in a dielectric layer on a semiconductor substrate, the dielectric layer having a first interlayer dielectric (ILD) layer over an etch stop layer, wherein the trench exposes top surfaces of a via feature and a second ILD layer surrounding the via feature, wherein the trench further exposes side surfaces of the first ILD layer and the etch stop layer, wherein the top surfaces of the via feature and the second ILD layer are coplanar, and wherein the via feature is disposed directly above a metal contact over the substrate;
forming a conductive barrier layer directly on the via feature, the ILD layer, and sidewalls of the trench;
forming a bottom metal feature of a first metal on the barrier layer, wherein the bottom metal feature is formed on a bottom portion of the trench;
depositing a liner of the first metal on the bottom metal feature and sidewalls of the barrier layer; and
forming a top metal feature of a second metal on the liner, wherein the top metal feature fills the trench, and wherein the first metal is cobalt, and the second metal is copper.
2 . The method of claim 1 , wherein the forming of the bottom metal feature includes:
depositing the first metal on the barrier layer to fill the trench;
performing a chemical-mechanical polishing (CMP) process to the first metal; and
etching back the first metal such that a top surface of the first metal is recessed from a top surface of the dielectric layer.
3 . The method of claim 1 , wherein the via feature includes a conductive material and wherein the liner and the barrier layer are different in composition.
4 . The method of claim 1 , wherein the forming of the top metal feature includes:
depositing the second metal on the liner to fill the trench; and
performing a CMP process to the second metal, the barrier layer, the liner, and the dielectric layer such that top surfaces of the dielectric layer, the barrier layer, the liner, and the second metal are coplanar.
5 . The method of claim 4 , wherein the depositing of the second metal includes:
depositing a seed layer; and
performing a plating process to deposit the second metal on the seed layer.
6 . The method of claim 1 , further comprising:
forming a fin active region extruded above the semiconductor substrate;
forming a gate stack disposed on a channel region of the fin active region, wherein the gate stack includes a gate dielectric layer and a gate electrode; and
forming source/drain (S/D) features on a S/D region of the fin active region and interposed by the gate stack,
wherein the S/D features are electrically connected to the via feature.
7 . The method of claim 6 , further comprising:
forming silicide layers over the S/D features, wherein the metal contact lands on one of the silicide layers over one of the S/D features, wherein the bottom metal feature is electrically connected to the metal contact.
8 . The method of claim 7 , wherein the via feature is landing on the metal contact and disposed between the barrier layer and the metal contact.
9 . The method of claim 1 , wherein the liner includes a bottom surface spanning a first width and the bottom metal feature includes a top surface spanning a second width being equal to the first width, and wherein the bottom surface of the liner is fully aligned with the top surface of the bottom metal feature.
10 . The method of claim 1 , further comprising:
forming source/drain (S/D) epitaxial features over the semiconductor substrate;
forming silicide features over the S/D epitaxial features;
forming the metal contact to land on the silicide features; and
forming the via feature to land on the metal contact, wherein the metal contact includes a barrier layer, a seed layer, and a fill layer, wherein the seed layer surrounds outer surfaces of the fill layer, and the barrier layer surrounds outer surfaces of the seed layer.
11 . A method, comprising:
forming a fin active region extruded above a semiconductor substrate;
forming a gate stack disposed on the fin active region, wherein the gate stack includes a high-k gate dielectric layer and a metal gate electrode having a filling metal layer;
forming source/drain (S/D) features on the fin active region and interposed by the gate stack;
forming a silicide feature on each of the S/D features;
forming an S/D contact landing on one of the silicide features, the S/D contact having a conductive core and a barrier liner surrounding bottom and side surfaces of the conductive core;
forming a via feature landing on the S/D contact;
forming a conductive feature landing on the via feature, wherein the forming of the conductive feature further includes:
depositing an interlayer dielectric (ILD) layer over the via feature, the ILD layer includes an etch stop layer over the S/D contact and a low-k dielectric layer over the etch stop layer;
forming a trench in the ILD layer, wherein the trench exposes a top surface of the S/D contact, a top surface of another ILD layer surrounding the S/D contact, a side surface of the etch stop layer, and a side surface of the low-k dielectric layer;
forming a barrier layer on sidewalls and a bottom surface of the trench;
forming a bottom metal feature of a first metal on the barrier layer, wherein the bottom metal feature is formed by filling the trench with the first metal and then recessing the first metal to expose a sidewall portion of the barrier layer;
depositing a liner of the first metal on the bottom metal feature and on the sidewall portion of the barrier layer; and
forming a top metal feature of a second metal on the liner, wherein the top metal feature fills the trench, and wherein the first metal is cobalt and the second metal is copper.
12 . The method of claim 11 , wherein
the barrier layer is surrounding both the top metal feature and the bottom metal feature;
the liner is surrounding the top metal feature and is separating the top metal feature from the bottom metal feature and the barrier layer; and
the barrier layer and the liner are different in composition.
13 . The method of claim 12 , wherein the barrier layer includes tantalum nitride.
14 . The method of claim 11 , wherein the liner includes a bottom surface spanning a first width and the bottom metal feature includes a top surface spanning a second width being equal to the first width, and wherein the bottom surface of the liner is fully aligned with the top surface of the bottom metal feature.
15 . A method, comprising:
forming a gate stack disposed on an active region of a semiconductor substrate;
forming a source/drain (S/D) feature on the active region and disposed on an edge of the gate stack;
forming a silicide feature on the S/D feature;
forming an S/D contact landing on the silicide feature;
forming a via feature landing on the S/D contact, the via feature having a top surface above a top surface of the S/D contact; and
forming a conductive feature landing on the via feature, wherein the conductive feature includes
a bottom metal feature of a first metal;
a top metal feature of a second metal over the bottom metal feature, wherein the second metal is different from the first metal in composition; and
a barrier layer surrounding both the top metal feature and the bottom metal feature, the barrier layer separating the via feature from the bottom metal feature, wherein a liner separates the top metal feature from the bottom metal feature and the barrier layer, wherein:
the barrier layer includes tantalum nitride and the liner includes cobalt,
the first metal is cobalt, and the second metal is copper,
the liner includes a bottom surface spanning a first width and the bottom metal feature includes a top surface spanning a second width being equal to the first width, and
the bottom surface of the liner is fully aligned with the top surface of the bottom metal feature.
16 . The method of claim 15 , wherein the forming of the conductive feature includes
depositing an interlayer dielectric (ILD) layer over the S/D feature and the gate stack, the ILD layer includes an etch stop layer over the via feature and a low-k dielectric layer over the etch stop layer;
forming a trench in the ILD layer, wherein the trench exposes a top surface of the via feature and side surfaces of the etch stop layer and the low-k dielectric layer;
forming the barrier layer on sidewalls and a bottom surface of the trench;
forming the bottom metal feature on the barrier layer, wherein the bottom metal feature is formed on a bottom portion of the trench;
depositing a liner on the bottom metal feature and sidewalls of the barrier layer; and
forming the top metal feature on the liner, wherein the top metal feature fills the trench, wherein a conductivity of the second metal is greater than that of the first metal.
17 . The method of claim 16 , wherein
the liner is surrounding the top metal feature; and
the barrier layer is surrounding the liner and the bottom metal feature.
18 . The method of claim 15 , wherein the top metal feature has a first thickness, the bottom metal feature has a second thickness, and a ratio of the second thickness to the first thickness ranges between about 0.5 to about 1.5.
19 . The method of claim 15 , wherein the S/D contact includes a barrier liner surrounding a conductive core.
20 . The method of claim 19 , wherein the S/D contact further includes a seed layer between the barrier liner and the conductive core.