Ferroelectric field effect transistors having enhanced memory window and methods of making the same
A ferroelectric transistor includes a semiconductor channel comprising a semiconductor material, a strained and/or defect containing ferroelectric gate dielectric layer located on a surface of the semiconductor channel, a source region located on a first end portion of the semiconductor channel, and a drain region located on a second end portion of the semiconductor channel.
1. A ferroelectric transistor, comprising:
an alternating stack of insulating layers and electrically conductive layers;
a memory stack assembly vertically extending through the alternating stack and comprising a semiconductor channel comprising a semiconductor material and a defect containing ferroelectric gate dielectric layer located on a surface of the semiconductor channel and comprising at least one of a noble gas element or nanoclusters of non-polar metallic element that does not form a ferroelectric oxide material upon combination with oxygen at an atomic percentage in a range from 0.01% to 10%;
a gate electrode located on the defect containing ferroelectric gate dielectric layer;
a source region located on a first end portion of the semiconductor channel; and
a drain region located on a second end portion of the semiconductor channel.
2. The ferroelectric transistor of claim 1 , wherein the defect containing ferroelectric gate dielectric layer comprises a polycrystalline ferroelectric dielectric material including at least one of lattice or grain boundary defects.
3. The semiconductor device of claim 2 , wherein:
the at least one of lattice or grain boundary defects comprise pinned grain boundaries;
the nanoclusters of the non-polar metallic element are present at the pinned grain boundaries at a higher atomic concentration than within grains of the defect containing ferroelectric gate dielectric layer; and
the non-polar metallic element comprises an element selected from Mg, Ga, In, Sc, Y, rare earth elements, Ti, Ca, Ta, Pt, Mo, Ag, or Au.
4. The semiconductor device of claim 3 , wherein the defect containing ferroelectric gate dielectric layer comprises atoms of a noble gas element.
5. The ferroelectric transistor of claim 1 , wherein:
the vertically-extending portion of the semiconductor channel vertically extends through a plurality of electrically conductive layers and through a plurality of insulating layers within the alternating stack;
one of the electrically conductive layers of the alternating stack comprises the gate electrode and additional electrically conductive layers of the alternating stack comprise additional gate electrodes; and
the defect containing ferroelectric gate dielectric layer vertically extends through a plurality of electrically conductive layers and through a plurality of insulating layers within the alternating stack.
6. The ferroelectric transistor of claim 1 , wherein the semiconductor channel is a portion of a single crystalline semiconductor layer.
7. The ferroelectric transistor of claim 6 , wherein a predominant fraction of an entire volume of the defect containing ferroelectric gate dielectric layer contacting the single crystalline semiconductor layer is in epitaxial alignment with a single crystalline semiconductor material of the single crystalline semiconductor layer.
8. The ferroelectric transistor of claim 7 , wherein:
the single crystalline semiconductor layer comprises a strained single crystalline semiconductor layer; and
the defect containing ferroelectric gate dielectric layer is laterally strained within a horizontal plane with an average horizontal lattice constant that differs from an average horizontal lattice constant in an unstrained state at least by 0.01%.
9. The ferroelectric transistor of claim 1 , wherein the defect containing ferroelectric gate dielectric layer comprises BiFeO 3 , barium titanate, lead titanate or orthorhombic phase hafnium oxide inserted with at least one of Mg, Ga, In, Sc, Y, rare earth elements, Ti, Ca, Ta, Pt, Mo, Ag, or Au.
10. The ferroelectric transistor of claim 1 , wherein:
the gate electrode comprises a portion of one of the electrically conductive layers within the alternating stack; and
the ferroelectric transistor comprises additional gate electrodes comprising portions of the electrically conductive layers within the alternating stack that are proximal to the vertically-extending portion of the semiconductor channel.
11. The ferroelectric transistor of claim 1 , wherein each of the electrically conductive layers within the alternating stack is in direct contact with a sidewall of the defect containing ferroelectric gate dielectric layer.
12. The ferroelectric transistor of claim 1 , further comprising a semiconductor layer comprising a horizontal top surface in direct contact with a bottom surface of the alternating stack, wherein a vertically-extending portion of the semiconductor channel extends along a vertical direction that is perpendicular to the horizontal top surface of the semiconductor layer through each of the electrically conductive layers within the alternating stack.
13. The ferroelectric transistor claim 12 , wherein:
an annular bottom surface of the defect containing ferroelectric gate dielectric layer contacts the semiconductor layer; and
the vertically-extending portion of the semiconductor channel has a tubular portion that extends vertically and contacts an inner cylindrical sidewall of the defect containing ferroelectric gate dielectric layer, and comprises a planar bottom portion adjoined to a bottom end of the tubular portion and contacting a top surface segment of the semiconductor layer.
14. The ferroelectric transistor of claim 12 , wherein:
the defect containing ferroelectric gate dielectric layer and a vertically-extending portion of the semiconductor channel are located within a memory opening that vertically extends through each layer within the alternating stack; and
a horizontally-extending portion of the semiconductor channel are located within a surface portion of the semiconductor layer.
15. The ferroelectric transistor of claim 14 , further comprising:
a source contact via structure vertically extending through each layer within the alternating stack and electrically isolated from each of the electrically conductive layers, wherein the source region is embedded in the semiconductor layer and contacts a bottom surface of the source contact via structure and adjoined to an end portion of the horizontally-extending portion of the semiconductor channel; and
a drain contact via structure located above the alternating stack and contacting a top surface of the drain region which is located at an upper end of the vertically-extending portion of the semiconductor channel.
16. The ferroelectric transistor of claim 1 , wherein:
the semiconductor channel comprises a single crystalline semiconductor material; and
a predominant fraction of an entire volume of the defect containing ferroelectric gate dielectric layer is in epitaxial alignment with the single crystalline semiconductor material.
17. A ferroelectric transistor, comprising:
a semiconductor channel comprising a semiconductor material;
a defect containing ferroelectric gate dielectric layer located on a surface of the semiconductor channel and comprising a noble gas element in a range from 0.01% to 10%;
a gate electrode located on the defect containing ferroelectric gate dielectric layer;
a source region located on a first end portion of the semiconductor channel; and
a drain region located on a second end portion of the semiconductor channel.
18. The ferroelectric transistor of claim 17 , further comprising:
an alternating stack of insulating layers and electrically conductive layers; and
a memory stack assembly vertically extending through the alternating stack and comprising a vertically-extending portion of the semiconductor channel and the defect containing ferroelectric gate dielectric layer.
19. The ferroelectric transistor of claim 18 , wherein:
a semiconductor layer is located below the alternating stack;
the semiconductor layer comprises a single crystalline semiconductor material;
the vertically-extending portion of the semiconductor channel is polycrystalline; and
the semiconductor channel comprises a horizontally-extending portion located in an upper portion of the semiconductor layer and adjoined to a bottom end of the vertically-extending portion of the semiconductor channel;
the source region is single crystalline and is located within the semiconductor layer; and
the drain region is located at an upper end of the vertically-extending portion of the semiconductor channel.
20. The ferroelectric transistor of claim 17 , wherein:
the semiconductor channel comprises a single crystalline semiconductor material; and
a predominant fraction of an entire volume of the defect containing ferroelectric gate dielectric layer is in epitaxial alignment with the single crystalline semiconductor material.