Three-dimensional ferroelectric memory device containing lattice-matched templates and methods of making the same
A ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and containing a vertical stack of memory elements and a vertical semiconductor channel. Each memory element within the vertical stack of memory elements includes a crystalline ferroelectric memory material portion and an epitaxial template portion.
1. A ferroelectric memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers;
a memory opening vertically extending through the alternating stack; and
a memory opening fill structure located in the memory opening and comprising a vertical stack of memory elements and a vertical semiconductor channel, wherein each memory element within the vertical stack of memory elements comprises a crystalline ferroelectric memory material portion and an epitaxial template portion,
wherein one of the electrically conductive layers comprise a horizontal top surface that is in direct contact with a horizontal bottom surface of an overlying insulating layer of the insulating layers.
2. The ferroelectric memory device of claim 1 , wherein the crystalline ferroelectric memory material portion is single crystalline.
3. The ferroelectric memory device of claim 1 , wherein the crystalline ferroelectric memory material portion is polycrystalline and each grain in the crystalline ferroelectric memory material portion is epitaxially aligned to a respective grain of the epitaxial template portion.
4. The ferroelectric memory device of claim 1 , wherein:
the crystalline ferroelectric memory material portion has an annular cylindrical shape; and
an inner cylindrical sidewall of the crystalline ferroelectric memory material portion contacts the vertical semiconductor channel.
5. The ferroelectric memory device of claim 1 , wherein the epitaxial template portion comprises an outer sidewall that contacts a cylindrical sidewall of the respective one of the electrically conductive layers.
6. A ferroelectric memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers;
a memory opening vertically extending through the alternating stack; and
a memory opening fill structure located in the memory opening and comprising a vertical stack of memory elements and a vertical semiconductor channel, wherein each memory element within the vertical stack of memory elements comprises a crystalline ferroelectric memory material portion and an epitaxial template portion,
wherein:
the epitaxial template portion comprises a material selected from yttria stabilized zirconia, indium tin oxide, lead iridium oxide, or a bilayer comprising titanium nitride and titanium oxide; and
the crystalline ferroelectric memory material portion comprises orthorhombic phase, doped hafnium oxide.
7. The ferroelectric memory device of claim 1 , wherein the crystalline ferroelectric memory material portion comprises orthorhombic phase hafnium zirconium oxide.
8. The ferroelectric memory device of claim 1 , wherein the crystalline ferroelectric memory material portion has a radial dipole moment that is parallel to or is antiparallel to a radial direction extending radially and horizontally from a vertical axis passing through a geometrical center of the memory opening.
9. The ferroelectric memory device of claim 1 , wherein the one of the electrically conductive layers comprises a horizontal bottom surface that is in direct contact with a horizontal top surface of an underlying insulating layer of the insulating layers.
10. The ferroelectric memory device of claim 1 , wherein:
each of the electrically conductive layers comprise a respective horizontal top surface that is in direct contact with a horizontal bottom surface of a respective overlying insulating layer of the insulating layers; and
each of the electrically conductive layers comprise a respective horizontal bottom surface that is in direct contact with a horizontal top surface of a respective underlying insulating layer of the insulating layers.
11. The ferroelectric memory device of claim 1 , further comprising:
a backside trench vertically extending through the alternating stack; and
a backside trench fill structure located in the backside trench, wherein each of the epitaxial template portions does not contact the backside trench fill structure, and is laterally spaced from the backside trench fill structure by portions of the electrically conductive layers.
12. The ferroelectric memory device of claim 1 , wherein each of the electrically conductive layers is located at a same level as and has a same vertical extent as a respective one of the epitaxial template portions.
13. The ferroelectric memory device of claim 1 , wherein each of the electrically conductive layers is located at a same level as and has a greater vertical extent than a respective one of the epitaxial template portions.
14. A ferroelectric memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers;
a memory opening vertically extending through the alternating stack; and
a memory opening fill structure located in the memory opening and comprising a vertical stack of memory elements and a vertical semiconductor channel, wherein each memory element within the vertical stack of memory elements comprises a crystalline ferroelectric memory material portion and an epitaxial template portion,
wherein the crystalline ferroelectric memory material portion is vertically spaced from an overlying one of the insulating layers and an underlying one of the insulating layers by horizontally-extending portions of the epitaxial template portion.
15. The ferroelectric memory device of claim 1 , further comprising a vertical stack of non-epitaxial dielectric material portions having a same material composition as the crystalline ferroelectric memory material portions and vertically interlaced with the vertical stack of memory elements, wherein the vertical stack of non-epitaxial dielectric material portions is not ferroelectric and is amorphous or polycrystalline with random crystallographic orientations.
16. A ferroelectric memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers;
a memory opening vertically extending through the alternating stack; and
a memory opening fill structure located in the memory opening and comprising a vertical stack of memory elements and a vertical semiconductor channel, wherein each memory element within the vertical stack of memory elements comprises a crystalline ferroelectric memory material portion and an epitaxial template portion,
wherein each memory element within the vertical stack of memory elements comprises a crystalline template structure contacting an outer cylindrical sidewall of the epitaxial template portion.
17. The ferroelectric memory device of claim 16 , wherein an outer sidewall of the crystalline template structure contacts a cylindrical sidewall of a respective one of the electrically conductive layers.
18. The ferroelectric memory device of claim 16 , wherein the crystalline template structure comprises yttria stabilized zirconia and the epitaxial template portion comprises indium tin oxide, lead iridium oxide or a bilayer comprising titanium nitride and titanium oxide.
19. The ferroelectric memory device of claim 6 , wherein the epitaxial template portion comprises the yttria stabilized zirconia.
20. The ferroelectric memory device of claim 6 , wherein the epitaxial template portion comprises the indium tin oxide.