Static random access memory with write assist adjustment
View Patent ↗The present disclosure describes embodiments of a write assist circuit. The write assist circuit can include a boost circuit configured to output a first negative voltage at a first output terminal, and an adjustment circuit configured to couple the first negative voltage to a second negative voltage higher than the first negative voltage. The adjustment circuit can include a transistor, and a second output terminal electrically connected to the first output terminal. The transistor can include a first source/drain terminal, a second source/drain terminal, and a gate terminal. The first source/drain terminal can be electrically coupled to the second output terminal. The second source/drain terminal can be electrically connected to a voltage source. The gate terminal can be electrically connected to a ground voltage supply.
1. A write assist circuit, comprising:
a boost circuit configured to output a first negative voltage at a first output terminal; and
an adjustment circuit configured to increase, at the first output terminal, the first negative voltage to a second negative voltage higher than the first negative voltage, wherein the adjustment circuit comprises a transistor and a second output terminal electrically connected to the first output terminal.
2. The write assist circuit of claim 1 , wherein the transistor comprises a first source/drain terminal electrically coupled to the second output terminal, a second source/drain terminal electrically connected to a voltage source, and a gate terminal electrically connected to a ground voltage source.
3. The write assist circuit of claim 2 , wherein the second source/drain terminal is electrically connected to the ground voltage source.
4. The write assist circuit of claim 2 , wherein the adjustment circuit further comprises a
multiplexer, wherein an input terminal of the multiplexer is electrically connected to the first source/drain terminal, and an output terminal of the multiplexer is electrically connected to the second output terminal.
5. The write assist circuit of claim 2 , wherein the voltage source is configured to provide a positive voltage.
6. The write assist circuit of claim 2 , wherein the adjustment circuit further comprises an other transistor, wherein:
the other transistor comprises an other gate terminal, an other first source/drain terminal, and an other second source/drain terminal;
the other gate terminal is electrically connected to ground;
the other first source/drain terminal is electrically connected to the voltage source; and
the other second source/drain terminal is electrically connected to the second source/drain terminal of the transistor.
7. The write assist circuit of claim 1 , wherein the adjustment circuit further comprises a plurality of transistors, wherein gate terminals of the plurality of transistors are electrically connected to a ground voltage source and source/drain terminals of the plurality of transistors are electrically connected to the second output terminal.
8. A memory device, comprising:
an array of memory cells;
a write driver circuit configured to provide a reference voltage; and
a write assist circuit configured to couple the reference voltage to a first negative voltage, wherein the write assist circuit comprises:
a boost circuit configured to provide a second negative voltage lower than the first negative voltage; and
an adjustment circuit comprising a transistor and configured to increase the second negative voltage to the first negative voltage.
9. The memory device of claim 8 , wherein each memory cell in the array of memory cells comprises a pass gate transistor, wherein a threshold voltage of the pass gate transistor is substantially equal to a threshold voltage of the transistor.
10. The memory device of claim 8 , wherein the transistor comprises a gate terminal electrically connected to ground.
11. The memory device of claim 8 , wherein:
the write driver circuit is configured to output the reference voltage at a bitline of the array of memory cells;
the boost circuit is configured to couple the reference voltage to the second negative voltage at the bitline; and
the adjustment circuit is configured to increase the second negative voltage to the first negative voltage at the bitline.
12. The memory device of claim 8 , wherein the transistor comprises:
a first source/drain terminal electrically connected to a voltage source configured to output a fixed logic high level; and
a second source/drain terminal electrically connected to the boost circuit and configured to couple the second negative voltage to the first negative voltage.
13. The memory device of claim 12 , wherein the adjustment circuit further comprises a multiplexer configured to electrically couple the second source/drain terminal to the boost circuit.
14. The memory device of claim 12 , wherein the adjustment circuit further comprises an other transistor, wherein:
the other transistor comprises an other gate terminal, an other first source/drain terminal, and an other second source/drain terminal;
the other gate terminal is electrically connected to ground;
the other first source/drain terminal is electrically connected to the voltage source; and
the other second source/drain terminal is electrically connected to the second source/drain terminal of the transistor.
15. The memory device of claim 12 , wherein the adjustment circuit further comprises an other transistor, wherein:
the other transistor comprises an other gate terminal, an other first source/drain terminal, and an other second source/drain terminal;
the other gate terminal is electrically connected to ground;
the other first source/drain terminal is electrically connected to the voltage source; and
the other second source/drain terminal is electrically connected to the boost circuit.
16. The memory device of claim 15 , wherein the adjustment circuit further comprises a multiplexer electrically connected to the second source/drain terminal of the transistor and to the other second source/drain terminal of the other transistor.
17. A method for a memory write operation, comprising:
providing a reference voltage to one or more bitlines coupled to one or more memory cells;
coupling the reference voltage to a first negative voltage at the one or more bitlines; and
increasing, at the one or more bitlines, the first negative voltage to a second negative voltage higher than the first negative voltage.
18. The method of claim 17 , wherein the providing the reference voltage comprises:
initializing the reference voltage to a ground level prior to coupling the reference voltage to the first negative voltage; and
increasing the first negative voltage to the second negative voltage.
19. The method of claim 17 , wherein the increasing the first negative voltage to the second negative voltage comprises biasing, via a voltage source configured to output a static logic low level, a gate terminal of one or more pull-up transistors to the static logic low level.
20. The method of claim 17 , wherein the increasing the first negative voltage to the second negative voltage comprises:
biasing a source terminal of one or more pull-up transistors; and
coupling, with a multiplexer, a drain terminal of each of the one or more pull-up transistors to the one or more bitlines with the second negative voltage.