IP Library › Granted Patent US 11,610,888
Granted Patent B2
US 11,610,888 · App. 17/326,005 · Granted Mar 21, 2023

Semiconductor device having cap layer

Inventors: Sung-Li Wang (Hsinchu County, TW); Pang-Yen Tsai (Hsinchu County, TW); Yasutoshi Okuno (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H01L27/0922H01L21/02636H01L21/76897H01L21/823814H01L21/823821H01L21/823871H01L27/092H01L27/0924H01L29/0847H01L29/45H01L29/456H01L29/7853H01L29/7854H01L21/31053H01L21/31111H01L21/3212H01L29/665H01L29/6653H01L29/66545
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Quick Facts
Patent No.
US 11,610,888
App. No.
17/326,005
Granted
Mar 21, 2023
Kind
B2
Abstract

A semiconductor device includes a semiconductive substrate, a semiconductive fin, an isolation structure, a source/drain epitaxial structure, a first cap layer, and a second cap layer. The semiconductive fin protrudes from the semiconductive substrate. The isolation structure is over the semiconductive substrate and laterally surrounds the semiconductive fin. The source/drain epitaxial structure is over the semiconductive fin. The source/drain epitaxial structure has a rounded corner extending laterally and a top above the rounded corner. The first cap layer extends from the rounded corner of the source/drain epitaxial structure to the top of the source/drain epitaxial structure. The second cap layer covers the rounded corner and a bottom of the source/drain epitaxial structure. The first and second cap layers are made of different materials.

Claims (39)

1. A semiconductor device comprising:

a semiconductive substrate;

a semiconductive fin protruding from the semiconductive substrate;

an isolation structure over the semiconductive substrate and laterally surrounding the semiconductive fin;

a source/drain epitaxial structure over the semiconductive fin, wherein the source/drain epitaxial structure has a rounded corner extending laterally and a top above the rounded corner;

a first cap layer extending from the rounded corner of the source/drain epitaxial structure to the top of the source/drain epitaxial structure;

a second cap layer covering the rounded corner and a bottom of the source/drain epitaxial structure, wherein the first and second cap layers are made of different materials; and

a contact over the second cap layer, wherein the first cap layer is a single piece of continuous material and in contact with the source/drain epitaxial structure, and the contact is in contact with a top surface of the first cap layer.

2. The semiconductor device of claim 1 , wherein the first cap layer comprises silicon.

3. The semiconductor device of claim 1 , wherein the second cap layer comprises silicon.

4. The semiconductor device of claim 1 , wherein the first cap layer and the second cap layer comprise different metals.

5. The semiconductor device of claim 1 , wherein the second cap layer is spaced apart from the top of the source/drain epitaxial structure.

6. The semiconductor device of claim 1 , wherein a bottommost surface of the source/drain epitaxial structure is lower than a bottommost surface of the second cap layer.

7. The semiconductor device of claim 1 , wherein the first cap layer comprises Ni, Co, Pt, W, Ru, or combinations thereof.

8. The semiconductor device of claim 1 , wherein the second cap layer comprises Ti, Er, Y, Yb, Eu, Tb, Lu, Th, Sc, Hf, Zr, Tb, Ta, or combinations thereof.

9. A semiconductor device comprising:

an isolation structure over a substrate;

a fin structure extending from the substrate and laterally surrounded by the isolation structure;

a source/drain epitaxial structure over the fin structure, wherein the source/drain epitaxial structure comprises a round corner directly above the isolation structure and a bottom under the round corner;

a first cap layer in contact with the round corner and the bottom of the source/drain epitaxial structure, wherein a topmost surface of the first cap layer is lower than a topmost surface of the source/drain epitaxial structure; and

a contact etch stop layer (CESL) covering the first cap layer.

10. The semiconductor device of claim 9 , wherein the first cap layer is a metal alloy layer.

11. The semiconductor device of claim 9 , further comprising a second cap layer over the source/drain epitaxial structure and in contact with the first cap layer.

12. The semiconductor device of claim 11 , wherein the second cap layer is a metal alloy layer.

13. The semiconductor device of claim 11 , wherein the CESL is in contact with the second cap layer.

14. The semiconductor device of claim 11 , wherein the first and second cap layers both comprise Si.

15. A semiconductor device comprising:

a substrate;

a fin structure protruding from the substrate;

an isolation structure laterally surrounding the fin structure;

a source/drain epitaxial structure over the fin structure;

a first cap layer in contact with a bottom of the source/drain epitaxial structure and spaced apart from the isolation structure;

a contact etch stop layer (CESL) in contact with the first cap layer and a top surface of the isolation structure; and

a contact covering and electrically connected to the source/drain epitaxial structure, wherein a bottommost surface of the contact is higher than a topmost surface of the first cap layer.

16. The semiconductor device of claim 15 , wherein the first cap layer comprises metals.

17. The semiconductor device of claim 15 , wherein a bottommost surface of the source/drain epitaxial structure is lower than the top surface of the isolation structure.

18. The semiconductor device of claim 15 , wherein the source/drain epitaxial structure has a rounded top.

19. The semiconductor device of claim 15 , wherein the source/drain epitaxial structure has a rounded corner directly above the isolation structure, and the first cap layer is in contact with the rounded corner of the source/drain epitaxial structure.

20. The semiconductor device of claim 15 , further comprising a second cap layer over and in contact with the source/drain epitaxial structure and the first cap layer, wherein the second cap layer comprises silicon.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 24, 2021
From: WANG, SUNG-LI; TSAI, PANG-YEN; OKUNO, YASUTOSHI
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 056329/0607 →
Continuity (4)
Continuation 16927799 · Jul 13, 2020
Continuation 16178340 · Nov 1, 2018
Provisional Application 62591133 · Nov 27, 2017
Related Publication 20210272956A1 · Sep 2, 2021