Three-dimensional semiconductor memory device including ferroelectric thin film and manufacturing method of the same

1. A method of manufacturing a three-dimensional semiconductor memory device including a ferroelectric thin film, the method comprising:

forming a mold structure including interlayer dielectric layers and sacrificial layers alternately stacked on a substrate;

forming channel holes penetrating the mold structure;

forming vertical channel structures inside the channel holes;

forming an isolation trench penetrating the mold structure and having a line shape extending in one direction;

selectively removing the sacrificial layers exposed by the isolation trench;

forming gate electrodes filling a space from which the sacrificial layers are removed; and

performing a heat treatment process and a cooling process for the vertical channel structures,

wherein the forming of the vertical channel structures comprises:

forming a data storage pattern configured to conformally cover an inner sidewall of each of the channel holes; and

forming a vertical semiconductor pattern covering a sidewall of the data storage pattern,

wherein the data storage pattern is formed of a ferroelectric thin film having a single-layer structure,

wherein a cooling rate of the cooling process is −180° C./sec to −90° C./sec.

2. The method of claim 1 , wherein the cooling process is quenching the vertical channel structures.

3. The method of claim 2 , wherein the quenching uses deionized water (DI water) from which ions are removed.

4. The method of claim 1 , wherein the heat treatment process comprises heating to a first temperature for a first time interval and maintaining the first temperature for a second time interval.

5. The method of claim 4 , wherein the first temperature is 350° C. to 900° C.,

wherein a ramping rate of the heat treatment process is 17.5° C./sec to 45° C./sec.

6. The method of claim 1 , wherein the heat treatment process and the cooling process are performed after the forming of the gate electrodes.

7. The method of claim 1 , further comprising:

forming a common source area in the substrate exposed by the isolation trench; and

forming an insulating spacer covering a sidewall of the isolation trench and a common source plug filling an internal space of the isolation trench surrounded by the insulating spacer.

8. The method of claim 1 , wherein the forming of the vertical channel structures further comprises recessing an upper portion of the vertical semiconductor pattern, and forming a conductive pad by filling a doped semiconductor material in a recessed area.

9. The method of claim 1 , further comprising forming lower epitaxial layers in lower portions of the channel holes between the forming of the channel holes and the forming of the vertical channel structures.