Semiconductor memory device
According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction.
1. A semiconductor memory device comprising:
a memory string extending in a first direction perpendicular to a substrate, the memory string having a first select transistor and memory cell transistors connected in series;
electrodes stacked in the first direction, the electrodes having a first select electrode connected to the first select transistor and control electrodes connected to the memory cell transistors;
a first length between the memory string and a first edge of the first select electrode in a second direction crossing the first direction that is smaller than a second length between the memory string and a second edge of one of the control electrodes in the second direction; and
a first slit extending in the first direction and the second direction and dividing the first select electrode in a third direction crossing the first direction and the second direction, a bottom of the first slit being under the one of the control electrodes and a third edge of the slit being between the first edge and the second edge in the second direction.
2. The semiconductor memory device according to claim 1 , further comprising:
a second select transistor, the first select transistor being between the second select transistor and the memory cell transistors;
a second select electrode connected to the second select transistor; and
a third length between the memory string and a fourth edge of the second select electrode in the second direction that is smaller than the first length.
3. The semiconductor memory device according to claim 2 , wherein the first edge and the fourth edge are configured as a one step staircase.
4. The semiconductor memory device according to claim 1 , wherein the control electrodes are configured as a first staircase in the second direction and a second staircase in the third direction.
5. The semiconductor memory device according to claim 4 , wherein the first staircase has more than one step and the second staircase has one step.
6. The semiconductor memory device according to claim 1 , further comprising:
a second select transistor, the first select transistor being between the second select transistor and the memory cell transistors;
a second select electrode connected to the second select transistor; and
a third length between the memory string and a fourth edge of the second select electrode in the second direction that is smaller than the first length, wherein
the first edge and the fourth edge are configured as a one step staircase; and
the control electrodes are configured as a more than one step staircase in the second direction and a one step staircase in the third direction.
7. The semiconductor memory device according to claim 1 , further comprising:
a second slit extending in the first direction and the second direction without dividing the first select electrode in the third direction, a fifth edge of the second slit being between the first edge and the second edge.
8. The semiconductor memory device according to claim 7 wherein, the fifth edge is between the third edge and the second edge.
9. The semiconductor memory device according to claim 7 , wherein
the control electrodes are configured as a first staircase in the second direction and a second staircase in the third direction; and
the second slit is between adjacent steps of the second staircase in the third direction.
10. The semiconductor memory device according to claim 7 , further comprising
a third slit extending in the first direction and the second direction, dividing the electrodes in the third direction.
11. The semiconductor memory device according to claim 7 , further comprising:
a conductive material in the second slit.
12. The semiconductor memory device according to claim 1 , further comprising:
a conductive material in the first slit.
13. A semiconductor memory device comprising:
a memory string extending in a first direction perpendicular to a substrate, the memory string having a first select transistor and memory cell transistors connected in series;
electrodes stacked in the first direction, the electrodes having a first select electrode connected to the first select transistor and control electrodes connected to the memory cell transistors;
a first length between the memory string and a first edge of the first select electrode in a second direction crossing the first direction that is smaller than a second length between the memory string and a second edge of one of the control electrodes in the second direction;
a first slit extending in the first direction and the second direction in a memory cell area and dividing the first select electrode in a third direction crossing the first direction and the second direction, a bottom of the first slit being under the one of the control electrodes and a third edge of the first slit being between the first edge and the second edge in the second direction; and
a second slit extending in the first direction and the second direction in a contact area without dividing the first select electrode in the third direction, a fifth edge of the second slit being between the first edge and the second edge.
14. The semiconductor memory device according to claim 13 , further comprising:
a second select transistor, the first select transistor being between the second select transistor and the memory cell transistors;
a second select electrode connected to the second select transistor; and
a third length between the memory string and a fourth edge of the second select electrode in the second direction that is smaller than the first length.
15. The semiconductor memory device according to claim 14 , wherein the first edge and the fourth edge are configured as a one step staircase.
16. The semiconductor memory device according to claim 13 , further comprising:
a second select transistor, the first select transistor being between the second select transistor and the memory cell transistors;
a second select electrode connected to the second select transistor; and
a third length between the memory string and a fourth edge of the second select electrode in the second direction that is smaller than the first length, wherein
the first edge and the fourth edge are configured as a one step staircase; and
the control electrodes are configured as a more than one step staircase in the second direction and a one step staircase in the third direction.
17. The semiconductor memory device according to claim 16 , wherein
the control electrodes are configured as a first staircase in the second direction and a second staircase in the third direction; and
the second slit is between adjacent steps of the second staircase in the third direction.
18. The semiconductor memory device according to claim 13 , further comprising
a third slit extending in the first direction and the second direction, dividing the electrodes in the third direction.
19. The semiconductor memory device according to claim 13 , further comprising:
a conductive material in the first slit.
20. The semiconductor memory device according to claim 13 , further comprising:
a conductive material in the second slit.