High-speed light sensing apparatus III
A circuit, including: a photodetector including a first readout terminal and a second readout terminal different than the first readout terminal; a first readout circuit coupled with the first readout terminal and configured to output a first readout voltage; a second readout circuit coupled with the second readout terminal and configured to output a second readout voltage; and a common-mode analog-to-digital converter (ADC) including: a first input terminal coupled with a first voltage source; a second input terminal coupled with a common-mode generator, the common-mode generator configured to receive the first readout voltage and the second readout voltage, and to generate a common-mode voltage between the first and second readout voltages; and a first output terminal configured to output a first output signal corresponding to a magnitude of a current generated by the photodetector.
1. A circuit, comprising:
a photodetector comprising a first readout terminal and a second readout terminal different than the first readout terminal;
a first readout subcircuit comprising a first MOSFET transistor and a second MOSFET transistor, the first MOSFET transistor comprising a first gate terminal coupled with a first control voltage source, a first channel terminal, and a second channel terminal coupled with the first readout terminal of the photodetector, and the second MOSFET transistor comprising a second gate terminal coupled with a second control voltage source, a third channel terminal coupled with a supply voltage node, and a fourth channel terminal coupled with the first channel terminal; and
a second readout subcircuit comprising a third MOSFET transistor and a fourth MOSFET transistor, the third MOSFET transistor comprising a third gate terminal coupled with the first control voltage source, a fifth channel terminal, and a sixth channel terminal coupled with the second readout terminal of the photodetector, and the fourth MOSFET transistor comprising a fourth gate terminal coupled with the second control voltage source, a seventh channel terminal coupled with the supply voltage node, and an eighth channel terminal coupled with the fifth channel terminal.
2. The circuit of claim 1 , wherein:
the first readout terminal is a first n-doped region;
the second readout terminal is a second n-doped region;
the first MOSFET transistor is a first n-type MOSFET transistor; and
the third MOSFET transistor is a second n-type MOSFET transistor.
3. The circuit of claim 2 , wherein:
the first n-doped region is partially or fully surrounded by a first p-well; and
the second n-doped region is partially or fully surrounded by a second p-well.
4. The circuit of claim 1 , wherein:
the first readout terminal is a first p-doped region;
the second readout terminal is a second p-doped region;
the first MOSFET transistor is a first p-type MOSFET transistor; and
the third MOSFET transistor is a second p-type MOSFET transistor.
5. The circuit of claim 4 , wherein:
the first p-doped region is partially or fully surrounded by a first n-well; and
the second p-doped region is partially or fully surrounded by a second n-well.
6. The circuit of claim 1 , wherein:
the first MOSFET is configured to generate a first voltage difference between the first channel terminal and the second channel terminal; and
the third MOSFET is configured to generate a second voltage difference between the fifth channel terminal and the sixth channel terminal.
7. The circuit of claim 1 , wherein:
the second MOSFET and the fourth MOSFET are configured to generate a first preset voltage on the fourth channel terminal and a second preset voltage on the eighth channel terminal respectively.
8. The circuit of claim 1 , further comprising:
a first source follower, coupled to the first channel terminal, configured to generate a first readout voltage; and
a second source follower, coupled to the second channel terminal, configured to generate a second readout voltage.
9. The circuit of claim 8 , further comprising:
a common-mode analog-to-digital converter, coupled to the first source follower and the second source follower, configured to generate a first digital output signal according to the first readout voltage and the second readout voltage.
10. The circuit of claim 8 , further comprising:
a differential-mode analog-to-digital converter, coupled to the first source follower and the second source follower, configured to generate a second digital output signal according to the first readout voltage and the second readout voltage.
11. A circuit, comprising:
a photodetector comprising a first readout terminal and a second readout terminal different than the first readout terminal; and
a first readout subcircuit comprising a first MOSFET transistor and a second MOSFET transistor, the first MOSFET transistor comprising a first gate terminal coupled with a first control voltage source, a first channel terminal, and a second channel terminal coupled with the first readout terminal of the photodetector, and the second MOSFET transistor comprising a second gate terminal coupled with a second control voltage source, a third channel terminal coupled with a supply voltage node, and a fourth channel terminal coupled with the first channel terminal.
12. The circuit of claim 11 , wherein:
the first readout terminal is a first n-doped region; and
the first MOSFET transistor is a first n-type MOSFET transistor.
13. The circuit of claim 12 , wherein:
the first n-doped region is partially or fully surrounded by a first p-well.
14. The circuit of claim 11 , wherein:
the first readout terminal is a first p-doped region; and
the first MOSFET transistor is a first p-type MOSFET transistor.
15. The circuit of claim 14 , wherein:
the first p-doped region is partially or fully surrounded by a first n-well.
16. The circuit of claim 11 , wherein:
during operation of the circuit, the first control voltage source generates a first control voltage configured to create a first voltage difference between a supply voltage of the supply voltage node and a first voltage of the first readout terminal.
17. The circuit of claim 11 , wherein:
the first MOSFET is configured to generate a first voltage difference between the first channel terminal and the second channel terminal.
18. The circuit of claim 11 , wherein:
the second MOSFET is configured to generate a first preset voltage on the fourth channel terminal.
19. The circuit of claim 11 , further comprising:
a first source follower, coupled to the first channel terminal, configured to generate a first readout voltage.