Method for preparing semiconductor memory device with air gaps for reducing capacitive coupling
The present disclosure provides a method for preparing a semiconductor memory device with air gaps for reducing capacitive coupling between a bit line and an adjacent conductive feature. The method includes forming an isolation member defining an active region in a substrate and a doped area in the active region; forming a gate structure in the substrate, wherein the gate structure divides the doped are into a first doped region and a second doped region; forming a bit line structure on the first doped region; forming an air gap adjacent to the bit line structure; forming a capacitor plug on the second doped region and a barrier layer on a sidewall of the capacitor plug; and forming a landing pad on a top portion of the capacitor plug, wherein the landing pad comprises a first silicide layer over the protruding portion and a second silicide layer on a sidewall of the barrier layer.
1. A method for preparing a semiconductor memory device, comprising:
forming an isolation member defining an active region in a substrate and a doped area in the active region, wherein the active region has a first P-type ion concentration in the substrate;
forming a gate structure in the substrate, wherein the gate structure divides the doped area into a first doped region and a second doped region;
forming a bit line structure on the first doped region;
forming an air gap adjacent to the bit line structure;
forming a capacitor plug on the second doped region and a barrier layer on a sidewall of the capacitor plug;
disposing a bit line spacer between the air gap and the barrier layer; and
forming a landing pad on a top portion of the capacitor plug, wherein the landing pad comprises a first silicide layer over the protruding portion and a second silicide layer on a sidewall of the barrier layer.
2. The method for preparing a semiconductor memory device of claim 1 , wherein forming the gate structure in the substrate comprises:
forming a gate trench in the substrate;
conformally forming a gate dielectric layer on inner sidewalls of the gate trench;
forming a lower gate electrode on the gate dielectric layer; and
forming an upper gate electrode disposed on the lower gate electrode, wherein the lower gate electrode has a relatively lower work function than the upper gate electrode.
3. The method for preparing a semiconductor memory device of claim 2 , wherein the lower gate electrode includes polysilicon is doped with an N-type ion, and the lower gate electrode is conformally disposed on the gate dielectric layer.
4. The method for preparing a semiconductor memory device of claim 2 , further comprising: conformally forming an intermediate gate electrode between the lower gate electrode and the upper gate electrode, wherein the intermediate gate electrode includes a barrier metal.
5. The method for preparing a semiconductor memory device of claim 2 , wherein the upper gate electrode includes a metal, a metal alloy, or a metal compound, and the upper gate electrode fills the gate trench and has a rail-like shape.
6. The method for preparing a semiconductor memory device of claim 2 , further comprising: forming a capping gate electrode covering an upper surface of the upper gate electrode, wherein the capping gate electrode includes a lower capping gate electrode and an upper capping gate electrode disposed on the lower capping gate electrode, and the lower capping gate electrode includes a barrier metal, and the upper capping gate electrode includes polysilicon doped with an N-type ion.
7. The method for preparing a semiconductor memory device of claim 1 , wherein forming the air gap adjacent to the bit line structure comprises:
forming a bit line capping layer surrounding an exposed surface of the bit line structure;
configuring the bit line spacer to have a first bit line spacer and a second bit line spacer, wherein the first bit line spacer and the second bit line spacer are disposed between the air gap and the barrier layer;
forming the first bit line spacer on sides of the bit line structure, with the bit line capping layer between the bit line structure and the first bit line spacer;
forming the second bit line spacer on sides of the first bit line spacer; and
performing an etching process to remove the first bit line spacer and to remain the second bit line spacer between the air gap and the barrier layer.
8. The method for preparing a semiconductor memory device of claim 1 , wherein forming the landing pad on a top portion of the capacitor plug comprises:
exposing a protruding portion of the capacitor plug and a top portion of the barrier layer;
forming a liner layer covering the capacitor plug and the barrier layer; and
performing a thermal process to form a landing pad over the dielectric layer, wherein the thermal process transforms a portion of the protruding portion and the liner layer into the first silicide layer, and the thermal process transforms a portion of the top portion of the barrier layers and the liner layer into the second silicide layer.
9. The method for preparing a semiconductor memory device of claim 1 , wherein after a thermal process, a top end of the second silicide layer is higher than a top end of the first silicide layer, and the second silicide layer surrounds the first silicide layer.
10. The method for preparing a semiconductor memory device of claim 1 , wherein the first silicide layer and the second silicide layer comprise polysilicon, the first silicide layer comprises tungsten, and the second silicide layer comprises titanium.