Thermally conductive structure for heat dissipation in semiconductor packages
A semiconductor package includes a wafer and at least one chip attached on first portions of an upper surface of the wafer. Further, the semiconductor package includes an insulating barrier layer, a thermally conductive layer, and a heat sink. The insulating barrier layer is arranged over the at least one chip attached on first portions of an upper surface of the wafer. The thermally conductive layer is arranged over the insulating barrier layer and at least partially encapsulates the at least one chip. The heat sink is arranged over the thermally conductive layer.
1. A semiconductor package, comprising:
a wafer;
at least one chip attached on first portions of an upper surface of the wafer;
an insulating barrier layer arranged over the at least one chip, the insulating barrier layer extending from over the at least one chip continuously over second portions of the upper surface of the wafer to an outer edge of the wafer;
a thermally conductive layer arranged over the insulating barrier layer, the thermally conductive layer at least partially encapsulating the at least one chip; and
a heat sink arranged over the thermally conductive layer, the heat sink having an outermost sidewall that is aligned with an outer sidewall of the insulating barrier layer at the outer edge of the wafer.
2. The semiconductor package of claim 1 , wherein the second portions of the upper surface of the wafer are continuously connected to the first portions of the upper surface of the wafer.
3. The semiconductor package of claim 1 , further comprising:
a thermal insulating material arranged between the thermally conductive layer and the heat sink.
4. The semiconductor package of claim 1 , wherein the thermally conductive layer is arranged directly over the at least one chip and is arranged along outer sidewalls of the at least one chip.
5. The semiconductor package of claim 1 , wherein the insulating barrier layer comprises a bottommost surface arranged below a topmost surface of the at least one chip.
6. The semiconductor package of claim 1 , wherein the at least one chip includes a first chip having a first chip height and a second chip having a second chip height different than the first chip height, wherein the first and second chip heights are measured perpendicular to the upper surface of the wafer.
7. The semiconductor package of claim 6 further comprising:
an adhesive layer arranged on the wafer, directly between the first chip and the wafer, and directly between the second chip and the wafer.
8. A semiconductor package, comprising:
a wafer;
a first chip and a second chip attached to an upper surface of the wafer, wherein an upper surface of the first chip is arranged at a first height measured perpendicularly from the upper surface of the wafer, wherein an upper surface of the second chip is arranged at a second height measured perpendicularly from the upper surface of the wafer, and wherein the first height is different than the second height;
an insulating barrier layer arranged over the wafer, above the upper surface of the first chip, along outer sidewalls of the first chip, above the upper surface of the second chip, and along sidewalls of the second chip;
a thermally conductive layer arranged over the insulating barrier layer;
a molding compound arranged over the thermally conductive layer, wherein the molding compound has thermal conductivity ranging from 0.6 W/m-K to 0.8 W/m-K, has a composition that differs from a composition of the thermally conductive layer, and contacts the insulating barrier layer over the first chip; and
a heat sink arranged over the thermally conductive layer.
9. The semiconductor package of claim 8 , wherein the thermally conductive layer has a planar upper surface that extends over an entirety of the upper surface of the wafer.
10. The semiconductor package of claim 8 , wherein the thermally conductive layer has a first thickness over the first chip and a second thickness over the second chip, wherein the first and second thicknesses are measured perpendicular to the upper surface of the wafer, and wherein the first thickness is different than the second thickness.
11. The semiconductor package of claim 8 , wherein a topmost surface of the insulating barrier layer is substantially coplanar with a topmost surface of the thermally conductive layer.
12. The semiconductor package of claim 8 , wherein the first chip is spaced apart from the second chip over the wafer by a portion of the wafer, and wherein the insulating barrier layer extends between the first chip and the second chip and over the portion of the wafer.
13. The semiconductor package of claim 8 , further comprising:
a thermal insulating material arranged between the thermally conductive layer and the heat sink.
14. The semiconductor package of claim 8 further comprising:
an adhesive layer arranged on the wafer, directly between the first chip and the wafer, and directly between the second chip and the wafer.
15. A semiconductor package, comprising:
a wafer having an adhesive layer on an upper surface of the wafer;
at least one chip attached on first portions of an upper surface of the adhesive layer;
an insulating barrier layer arranged over the at least one chip and directly on a second portion of the upper surface of the adhesive layer;
a thermally conductive layer arranged over the insulating barrier layer, arranged over the at least one chip, and having a substantially planar upper surface;
a molding compound extending along outer sidewalls of the thermally conductive layer, wherein the molding compound has a composition that differs from a composition of the thermally conductive layer; and
a heat sink arranged over the thermally conductive layer and having an outer sidewall aligned with an outer sidewall of the molding compound.
16. The semiconductor package of claim 15 , further comprising:
a thermal insulating material arranged between the thermally conductive layer and the heat sink.
17. The semiconductor package of claim 15 , wherein the thermally conductive layer is arranged along outer sidewalls of the at least one chip.
18. The semiconductor package of claim 15 , wherein the at least one chip includes a first chip having a first chip height and a second chip having a second chip height different than the first chip height, wherein the first and second chip heights are measured perpendicular to the upper surface of the wafer.
19. The semiconductor package of claim 18 , wherein the thermally conductive layer extends over and between the first and second chips, and wherein the substantially planar upper surface extends over the entirety of the upper surface of the wafer.
20. The semiconductor package of claim 18 , wherein the first chip is spaced apart from the second chip by the second portion of the upper surface of the adhesive layer.