Semiconductor memory device having spacer capping pattern disposed between burried dielectic pattern and an air gap and method of fabricating same
A semiconductor memory device includes; a first impurity region and a second impurity region spaced apart in a semiconductor substrate, a bit line electrically connected to the first impurity region, a storage node contact electrically connected to the second impurity region, an air gap between the bit line and the storage node contact, a landing pad electrically connected to the storage node contact, a buried dielectric pattern on a sidewall of the landing pad and on the air gap, and a spacer capping pattern between the buried dielectric pattern and the air gap.
1. A semiconductor memory device comprising:
a first impurity region and a second impurity region spaced apart in a semiconductor substrate;
a bit line electrically connected to the first impurity region;
a storage node contact electrically connected to the second impurity region;
an air gap between the bit line and the storage node contact;
a landing pad electrically connected to the storage node contact;
a buried dielectric pattern on a sidewall of the landing pad and on the air gap; and
a spacer capping pattern disposed between the buried dielectric pattern and the air gap in a direction perpendicular to the semiconductor substrate.
2. The semiconductor memory device of claim 1 , further comprising:
a first spacer and a second spacer between the bit line and the storage node contact, wherein:
the first spacer is adjacent to a sidewall of the bit line,
the second spacer is adjacent to a sidewall of the storage node contact, and
the air gap is between the first spacer and the second spacer.
3. The semiconductor memory device of claim 1 , wherein the spacer capping pattern and the buried dielectric pattern include different materials.
4. The semiconductor memory device of claim 1 , wherein the spacer capping pattern includes a dielectric material.
5. The semiconductor memory device of claim 2 , wherein:
a lowermost surface of the spacer capping pattern is above a level of a top surface of the bit line, and
an uppermost surface of the first spacer is above the level of the lowermost surface of the spacer capping pattern.
6. The semiconductor memory device of claim 1 , wherein a top surface of the storage node contact is below a level of a lowermost surface of the spacer capping pattern.
7. The semiconductor memory device of claim 1 , further comprising:
a conductive barrier layer between the storage node contact and the landing pad, wherein
the conductive barrier layer is in contact with the spacer capping pattern.
8. The semiconductor memory device of claim 1 , wherein:
the buried dielectric pattern includes an upper buried dielectric pattern and a lower buried dielectric pattern,
the spacer capping pattern is between the lower buried dielectric pattern and the air gap, and
the spacer capping pattern extends along a lateral surface of the lower buried dielectric pattern to contact a bottom surface of the upper buried dielectric pattern.
9. The semiconductor memory device of claim 8 , wherein the lower buried dielectric pattern is between the spacer capping pattern and the upper buried dielectric pattern.
10. A semiconductor memory device comprising:
a first impurity region in a semiconductor substrate;
a plurality of second impurity regions in the semiconductor substrate and spaced apart from each other across the first impurity region;
a bit line electrically connected to the first impurity region;
a plurality of storage node contacts electrically connected to corresponding second impurity regions;
a plurality of air gaps on opposite sides of the bit line, each of the air gaps being between the bit line and a corresponding one of the storage node contacts;
a plurality of landing pads electrically connected to corresponding storage node contacts;
a buried dielectric pattern between the landing pads and on one of the air gaps; and
a spacer capping pattern disposed between the buried dielectric pattern and the one of the air gaps in a direction perpendicular to the semiconductor substrate.
11. The semiconductor memory device of claim 10 , wherein each one of the plurality of air gaps comprises:
a first air gap between the bit line and one of the storage node contacts, wherein the first air gap is not covered by the spacer capping pattern; and
a second air gap between the bit line and another one of the storage node contacts, wherein the second air gap is covered by the spacer capping pattern.
12. The semiconductor memory device of claim 10 , wherein the spacer capping pattern and the buried dielectric pattern include different materials.
13. The semiconductor memory device of claim 10 , wherein the spacer capping pattern includes a dielectric material.
14. The semiconductor memory device of claim 10 , wherein respective top surfaces of the plurality of storage node contacts are disposed below a lowermost surface of the spacer capping pattern.
15. The semiconductor memory device of claim 10 , wherein:
the buried dielectric pattern includes an upper buried dielectric pattern and a lower buried dielectric pattern,
the spacer capping pattern is between the lower buried dielectric pattern and the one of the air gaps, and
the spacer capping pattern extends along a lateral surface of the lower buried dielectric pattern to contact a bottom surface of the upper buried dielectric pattern.
16. The semiconductor memory device of claim 15 , wherein the lower buried dielectric pattern is between the spacer capping pattern and the upper buried dielectric pattern.
17. The semiconductor memory device of claim 16 , further comprising:
a conductive barrier layer between each of the storage node contacts and a corresponding one of the landing pads, wherein
the conductive barrier layer is in contact with the spacer capping pattern.
18. The semiconductor memory device of claim 15 , further comprising a bottom electrode on each of the landing pads.
19. A semiconductor memory device comprising:
a first impurity region in a semiconductor substrate;
a plurality of second impurity regions in the semiconductor substrate and spaced apart from each other across the first impurity region;
a bit line electrically connected to the first impurity region;
a plurality of storage node contacts electrically connected to corresponding second impurity regions;
a plurality of air gaps on opposite sides of the bit line, each of the air gaps being between the bit line and a corresponding one of the storage node contacts;
a plurality of landing pads electrically connected to corresponding storage node contacts;
a buried dielectric pattern between the landing pads and on one of the air gaps;
a spacer capping pattern disposed between the buried dielectric pattern and the one of the air gaps in a direction perpendicular to the semiconductor substrate; and
a first spacer and a second spacer spaced apart from each other across each one of the plurality of air gaps, wherein:
the first spacer is adjacent to the bit line,
the second spacer is adjacent to the storage node contact,
a lowermost surface of the spacer capping pattern is above a top surface of the bit line, and
an uppermost surface of the first spacer is above the lowermost surface of the spacer capping pattern.
20. The semiconductor memory device of claim 19 , wherein:
a top surface of the second spacer is above a top surface of the bit line, and
a top surface of the first spacer is above the top surface of the second spacer.