Pixel array area optimization using stacking scheme for hybrid image sensor with minimal vertical interconnects
Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed.
1. An imaging sensor comprising:
a plurality of substrates including at least a first substrate and a second substrate;
wherein the first substrate comprises a pixel array comprising a plurality of pixel columns;
wherein the second substrate comprises a plurality of supporting circuits comprising a plurality of circuit columns;
wherein at least one pixel column at least partially overlaps at least one circuit column;
a plurality of pixel column buses and a plurality of circuit column buses;
wherein one or more of the pixel column buses has a first shape and one or more of the circuit column buses has a second shape that is different from the first shape;
a plurality of interconnects, wherein at least one interconnect provides for electrical communication between one circuit column bus and at least one pixel column bus;
wherein at least a portion of each of the plurality of pixel column buses is superimposed with at least a portion of one or more circuit column buses;
wherein said at least one interconnect is located anywhere along the superimposition of one pixel column bus and one corresponding circuit column bus.
2. The imaging sensor of claim 1 , wherein the first shape of the one or more pixel column buses is a linear shape.
3. The imaging sensor of claim 1 , wherein the second shape of the one or more circuit column buses is a linear shape.
4. The imaging sensor of claim 1 , wherein the second shape of the one or more circuit column buses is a u-shape.
5. The imaging sensor of claim 1 , wherein the one or more circuit column buses have a shape comprising a plurality of legs;
wherein each leg of the plurality of legs is superimposed with at least a portion of one or more pixel column buses.
6. The imaging sensor of claim 5 , wherein each leg of the plurality of legs of the circuit column bus is superimposed with a different pixel column bus of the plurality of pixel column buses.
7. The imaging sensor of claim 6 , wherein the electrical connection between one pixel column bus and one circuit column bus is accomplished by a single interconnect disposed on one of the plurality of legs of the one circuit column bus at a portion where the one pixel column bus and the one circuit column bus are superimposed with each other.
8. The imaging sensor of claim 6 , wherein the electrical connection between one pixel column bus and one circuit column bus is accomplished by two interconnects disposed on one or more of the plurality of legs of the one circuit column bus at a portion where the one pixel column bus and the one circuit column bus are superimposed with each other.
9. The imaging sensor of claim 6 , comprising:
a first circuit column comprising a first circuit column bus comprising a first leg and a second leg;
a second circuit column comprising a second circuit column bus comprising a first leg and a second leg;
a first pixel column comprising a first pixel column bus; and
a second pixel column comprising a second pixel column bus;
wherein the first pixel column is connected by a first interconnect to the first leg of the first circuit column bus; and
wherein the second pixel column is connected by a second interconnect to the second leg of the second circuit column bus.
10. The imaging sensor of claim 9 , wherein, on the second substrate, the first leg of the first circuit column bus is in substantial alignment with the first leg of the second circuit column bus; and
wherein, on the second substrate, the second leg of the first circuit column bus is in substantial alignment with the second leg of the second circuit column bus.
11. The imaging sensor of claim 10 , wherein the first circuit column is adjacent to the second circuit column in a first direction; and
wherein the first pixel column is adjacent to the second pixel column in a second direction perpendicular to the first direction.
12. The imaging sensor of claim 6 , comprising:
a circuit subgroup comprising a plurality of circuit columns arranged adjacent to each other on the second substrate in a first direction, wherein each circuit column includes a circuit column bus;
a pixel subgroup comprising a plurality of pixel columns arranged adjacent to each other on the first substrate in a second direction perpendicular to the first direction, wherein each pixel column includes a pixel column bus;
wherein each circuit column bus comprises a number of legs that is equal to a number of circuit columns in the circuit subgroup;
wherein each pixel column bus is connected by an interconnect to at least one circuit column bus of the plurality of circuit columns; and
wherein each pixel column bus of the pixel subgroup is connected by an interconnect to a different respective leg of a corresponding circuit column bus than other pixel column buses of the plurality of pixel columns.
13. The imaging sensor of claim 12 , wherein each pixel column overlaps a plurality of circuit columns; and
wherein each circuit column overlaps a plurality of pixel columns.
14. The imaging sensor of claim 12 , wherein each circuit column in the row of circuit columns at least partially overlaps each pixel column that is connected to a circuit column in the row of circuit columns.
15. The imaging sensor of claim 14 , wherein the imaging sensor comprises a plurality of rows of circuit columns; and
wherein each row of circuit columns is connected to a number of pixel columns corresponding to the number of legs in each circuit column bus of each circuit column in the row of circuit columns.
16. The imaging sensor of claim 5 , wherein said first substrate and said plurality of subsequent supporting substrates are stacked so that a plurality of communication columns are formed in a multi-layer stack.
17. The imaging sensor of claim 1 , wherein said pixel array covers twenty-five percent to ninety-nine percent of a surface of said first substrate.
18. The imaging sensor of claim 1 , wherein said second substrate is disposed behind said pixel array relative to an object to be imaged, and wherein said second substrate is in a stacked configuration with said first substrate.
19. The imaging sensor of claim 1 , wherein said second substrate is disposed behind said first substrate and displaced laterally therefrom.
20. The imaging sensor of claim 1 , wherein an area of one of said pixel columns on said first substrate is substantially equal to an area of one of said corresponding circuit columns on said second substrate.