IP Library › Granted Patent US 11,710,795
Granted Patent B2
US 11,710,795 · App. 17/183,670 · Granted Jul 25, 2023

Semiconductor device comprising oxide semiconductor with c-axis-aligned crystals

Inventor: Shunpei Yamazaki (Setagaya, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/7869H01L21/02554H01L21/02565H01L21/02631H01L29/04H01L29/045H01L29/221H01L29/2206H01L29/24H01L29/263H01L29/42356H01L29/45H01L29/4908H01L29/66969H01L29/78693H01L29/78696
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,710,795
App. No.
17/183,670
Granted
Jul 25, 2023
Kind
B2
Abstract

An embodiment is a semiconductor device which includes a first oxide semiconductor layer over a substrate having an insulating surface and including a crystalline region formed by growth from a surface of the first oxide semiconductor layer toward an inside; a second oxide semiconductor layer over the first oxide semiconductor layer; a source electrode layer and a drain electrode layer which are in contact with the second oxide semiconductor layer; a gate insulating layer covering the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating layer and in a region overlapping with the second oxide semiconductor layer. The second oxide semiconductor layer is a layer including a crystal formed by growth from the crystalline region.

Claims (59)

1. A semiconductor device comprising:

an electrode over a substrate;

a first insulating layer;

an oxide semiconductor layer overlapping with the electrode with the first insulating layer provided therebetween;

a source electrode and a drain electrode electrically connected to the oxide semiconductor layer;

a second insulating layer over the source electrode and the drain electrode and in contact with the oxide semiconductor layer; and

a third insulating layer over the second insulating layer,

wherein:

the oxide semiconductor layer comprises a first region and a second region, the first region being closer to the substrate than the second region,

the second region comprises a crystalline region, and

the crystalline region includes crystals whose c-axes are aligned.

2. The semiconductor device according to claim 1 , wherein side surfaces of the oxide semiconductor layer are covered by the source electrode and the drain electrode.

3. The semiconductor device according to claim 1 , further comprising a conductive layer overlapping with the electrode,

wherein the conductive layer comprises an indium zinc oxide.

4. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer comprises a channel formation region.

5. The semiconductor device according to claim 1 ,

wherein the oxide semiconductor layer comprises a material represented by InGa x Zn y O z where each of x, y, and z is an arbitrary number other than zero, and

wherein at least one of x, y, and z is a non-integer number.

6. The semiconductor device according to claim 1 , wherein the second region has a higher electric conductivity than the first region.

7. A semiconductor device comprising:

a gate electrode over a glass substrate;

a gate insulating layer over the gate electrode;

an oxide semiconductor layer over the gate insulating layer;

a source electrode and a drain electrode electrically connected to the oxide semiconductor layer;

a first insulating layer over the source electrode and the drain electrode and in contact with the oxide semiconductor layer; and

a second insulating layer over the first insulating layer,

wherein:

the gate electrode has a two-layer structure,

each of the source electrode and the drain electrode has a three-layer structure,

the oxide semiconductor layer comprises a first oxide semiconductor layer and a second oxide semiconductor layer,

the first oxide semiconductor layer comprises a first crystalline region,

the second oxide semiconductor layer comprises a second crystalline region, and

one of the first crystalline region and the second crystalline region includes crystals whose c-axes are aligned.

8. The semiconductor device according to claim 7 , wherein side surfaces of the oxide semiconductor layer are covered by the source electrode and the drain electrode.

9. The semiconductor device according to claim 7 , further comprising a conductive layer overlapping with the gate electrode,

wherein the conductive layer comprises an indium zinc oxide.

10. The semiconductor device according to claim 7 , wherein the oxide semiconductor layer comprises a channel formation region.

11. The semiconductor device according to claim 7 ,

wherein the oxide semiconductor layer comprises a material represented by InGa x Zn y O z where each of x, y, and z is an arbitrary number other than zero, and

wherein at least one of x, y, and z is a non-integer number.

12. A semiconductor device comprising:

a gate electrode over a glass substrate;

a gate insulating layer over the gate electrode;

an oxide semiconductor layer, comprising a material represented by InGa x Zn y O z where each of x, y, and z is an arbitrary number other than zero, over the gate insulating layer;

a source electrode and a drain electrode electrically connected to the oxide semiconductor layer;

a first insulating layer over the source electrode and the drain electrode and in contact with the oxide semiconductor layer; and

a second insulating layer over the first insulating layer,

wherein:

the gate electrode has a two-layer structure, one of two layers of the two-layer structure comprising aluminum and the other of the two layers of the two-layer structure comprising molybdenum,

each of the source electrode and the drain electrode has a three-layer structure, the three-layer structure comprising a first layer comprising titanium, a second layer comprising aluminum, and a third layer comprising titanium,

the oxide semiconductor layer comprises a first oxide semiconductor layer and a second oxide semiconductor layer,

the first oxide semiconductor layer comprises a first region and a second region, the first region being closer to the glass substrate than the second region,

the second region comprises a crystalline region, and

the crystalline region has c-axis aligned in a direction perpendicular to a surface of the oxide semiconductor layer.

13. The semiconductor device according to claim 12 , wherein side surfaces of the oxide semiconductor layer are covered by the source electrode and the drain electrode.

14. The semiconductor device according to claim 12 , further comprising a conductive layer overlapping with the gate electrode,

wherein the conductive layer comprises an indium zinc oxide.

15. The semiconductor device according to claim 12 , wherein the oxide semiconductor layer comprises a channel formation region.

16. The semiconductor device according to claim 12 , wherein at least one of x, y, and z is a non-integer number.

Priority Claims (1)
JP 2009-270857 · Nov 28, 2009 · national
Continuity (8)
Continuation 16812546 · Mar 9, 2020
Continuation 16272287 · Feb 11, 2019
Continuation 15882139 · Jan 29, 2018
Continuation 14964950 · Dec 10, 2015
Continuation 14330597 · Jul 14, 2014
Continuation 13684290 · Nov 23, 2012
Continuation 12951249 · Nov 22, 2010
Related Publication 20210202746A1 · Jul 1, 2021
Cited By (1)
US 12,402,360