Systems and methods for adjusting threshold voltage distribution due to semi-circle SGD
The following disclosure is directed to mitigating issues related to semi-circle drain side select gate (SC-SGD) memory holes in memory structures. When a memory hole is cut, the channel and the charge trap layer of the memory hole cut. Further, the outer dielectric layer (used to shield the channel and the charge trap layer) is cut and partially removed. When the selected SC-SGD is selected for an operation (e.g., programming), the channel and the charge trap layer are exposed to neighboring electrical field from bias voltage applied to an unselected SC-SGD. To prevent or mitigate the effects of this electrical field, a negative bias voltage is applied to the unselected SC-SGD. Additionally, this disclosure is directed to self-compensating techniques for SC-SGD. For example, the memory structure can utilize the neighboring electric field during verify, program, and read operations, whether the neighboring electric field is relatively strong or weak.
1. A method for accessing a memory device, the method comprising:
during a sensing operation, biasing, using a first voltage, a first semi-circular drain side select gate (SC-SGD), wherein the first SC-SGD is located on a first edge of an etched region; and
during the sensing operation, biasing, using a second voltage that is less than the first voltage, a second SC-SGD, wherein second SC-SGD is located on a second edge of the etched region opposite the first edge.
2. The method according to claim 1 , wherein the second voltage comprises a negative voltage.
3. The method according to claim 2 , wherein the etched region comprises a shallow hole etch (SHE) cut.
4. The method according to claim 1 , wherein, during a programming operation to program the first SC-SGD, the method further comprises:
providing a program pulse to the first SC-SGD; and
applying a positive bias voltage on the second SC-SGD.
5. A method for accessing a memory device, the method comprising:
biasing, using a first voltage, a first semi-circular drain side select gate (SC-SGD), wherein the first SC-SGD is located on a first edge of an etched region; and
biasing, using a second voltage that is less than the first voltage, a second SC-SGD, wherein second SC-SGD is located on a second edge of the etched region opposite the first edge, and
wherein, during a read operation, the method further comprises:
selecting, using the first SC-SGD, a string to read;
biasing, using a read voltage, the first SC-SGD; and
biasing, using a negative read voltage, the second SC-SGD.
6. The method according to claim 5 , wherein the second voltage comprises a negative voltage.
7. The method according to claim 6 , wherein the etched region comprises a shallow hole etch (SHE) cut.
8. A memory system, comprising:
a memory device; and
a controller operatively coupled to the memory device, the controller being configured to:
bias, using a first voltage, a first semi-circular drain side select gate (SC-SGD), wherein the first SC-SGD is located on a first edge of an etched region; and
bias, using a second voltage that is less than the first voltage, a second SC-SGD, wherein the second SC-SGD is located on a second edge of the etched region opposite the first edge.
9. The memory system according to claim 8 , wherein the second voltage comprises a negative voltage.
10. The memory system according to claim 9 , wherein the etched region comprises a shallow hole etch (SHE) cut.
11. The memory system according to claim 8 , wherein, during a programming operation to program the first SC-SGD, the controller being configured to:
provide a program pulse to the first SC-SGD; and
apply a positive bias voltage on the second SC-SGD.
12. The memory system according to claim 8 , wherein, during a read operation, the controller being configured to:
select, using the first SC-SGD, a string to read;
bias, using a read voltage, the first SC-SGD; and
bias, using a negative read voltage, the second SC-SGD.