Integrated circuit device and method of manufacturing the same

1. A semiconductor device comprising:

a substrate;

a bit line on the substrate, the bit line extending in a first direction that is parallel to a top surface of the substrate, and including a metal layer;

an insulation capping structure on the bit line, the insulation capping structure including a first insulation capping pattern, a second capping insulation pattern that is on the first insulation capping pattern, a third insulation capping pattern that is on the second insulation capping pattern, and a fourth insulation capping pattern that is on the third insulation capping pattern;

a contact plug arranged adjacent to the bit line;

a landing pad arranged on the contact plug, and extending on the insulation capping structure, the landing pad including a first portion, and a second portion that is on the first portion; and

a bit line spacer arranged between the bit line and the contact plug, and extending on a side of the insulation capping structure,

wherein a bottom surface of the first insulation capping pattern of the insulation capping structure contacts the metal layer of the bit line, and

a top surface of the fourth insulation capping pattern of the insulation capping structure contacts a bottom surface of the second portion of the landing pad.

2. The semiconductor device of claim 1 , wherein the landing pad includes a barrier layer and a conductive layer.

3. The semiconductor device of claim 1 , wherein a top surface of the bit line spacer contacts the bottom surface of the second portion of the landing pad.

4. The semiconductor device of claim 1 , wherein the bit line spacer includes oxide, and/or nitride.

5. The semiconductor device of claim 1 , wherein a lower width of the first portion of the landing pad in a second direction that is parallel to the top surface of the substrate and that is perpendicular to the first direction is greater than an upper width of the contact plug in the second direction.

6. The semiconductor device of claim 1 , wherein a top surface of the first portion of the landing pad is substantially coplanar with the top surface of the fourth insulation capping pattern of the insulation capping structure, and/or a top surface of the bit line spacer.

7. The semiconductor device of claim 1 , wherein each of the first to fourth insulation capping patterns of the insulation capping structure includes silicon nitride.

8. The semiconductor device of claim 1 , wherein the metal layer of the bit line includes tungsten (W).

9. The semiconductor device of claim 1 , wherein the metal layer of the bit line includes

nitrogen.

10. The semiconductor device of claim 1 , wherein the bit line spacer contacts a side surface of each of the first to fourth insulation capping patterns of the insulation capping structure.

11. A semiconductor device comprising:

a substrate including a cell region and a peripheral region;

a cell conductive line arranged in the cell region of the substrate, and including a first metal layer;

a cell insulation capping structure on the cell conductive line;

a peripheral conductive line arranged in the peripheral region of the substrate, and including a second metal layer;

a peripheral insulation capping structure on the peripheral conductive line;

a first wiring arranged on a side of the cell insulation capping structure and extending on a top surface of the cell insulation capping structure; and

a second wiring on the peripheral insulation capping structure,

wherein the cell insulation capping structure comprises:

a first cell insulation capping pattern;

a second cell insulation capping pattern on the first cell insulation capping pattern;

a third cell insulation capping pattern on the second cell insulation capping pattern; and

a fourth cell insulation capping pattern on the third cell insulation capping pattern, wherein the first cell insulation capping pattern of the cell insulation capping structure contacts the first metal layer of the cell conductive line, and

the fourth cell insulation capping pattern of the cell insulation capping structure contacts the first wiring, and

wherein the peripheral insulation capping structure comprises:

a first peripheral insulation capping pattern;

a second peripheral insulation capping pattern on the first peripheral insulation capping pattern;

a third peripheral insulation capping pattern on the second peripheral insulation capping pattern; and

a fourth peripheral insulation capping pattern on the third peripheral insulation capping pattern,

wherein the first peripheral insulation capping pattern of the peripheral insulation capping structure contacts the second metal layer of the peripheral conductive line, and

the fourth peripheral insulation capping pattern of the peripheral insulation capping structure contacts the second wiring.

12. The semiconductor device of claim 11 , wherein each of the first to fourth cell insulation capping patterns of the cell insulation capping structure includes silicon nitride, and

each of the first to fourth peripheral insulation capping patterns of the peripheral insulation capping structure includes silicon nitride.

13. The semiconductor device of claim 11 , wherein the first wiring includes the same material as that of the second wiring.

14. The semiconductor device of claim 11 , further comprising a cell conductive line spacer that is between the cell insulation capping structure and the first wiring,

wherein the cell conductive line spacer contacts the first to fourth cell insulation capping patterns of the cell insulation capping structure.

15. A semiconductor device comprising:

a substrate including a device isolation layer defining a first active region and a second active region;

a bit line structure on the first active region of the substrate, the bit line structure including a conductive line pattern and an insulation capping pattern that is on the conductive line pattern, the conductive line pattern including a metal layer;

a contact plug arranged adjacent to the bit line structure, and arranged on the second active region and on the device isolation layer;

a landing pad arranged on the contact plug and extending on the insulation capping pattern of the bit line structure; and

a bit line spacer arranged between the conductive line pattern of the bit line structure and the contact plug, and extending on a side of the insulation capping pattern of the bit line structure,

wherein the insulation capping pattern of the bit line structure comprises:

a first insulation capping pattern;

a second insulation capping pattern on the first insulation capping pattern;

a third insulation capping pattern on the second insulation capping pattern; and

a fourth insulation capping pattern on the third insulation capping pattern,

wherein the first insulation capping pattern of the insulation capping pattern of the bit line structure contacts the metal layer of the conductive line pattern of the bit line structure,

the fourth insulation capping pattern of the insulation capping pattern of the bit line structure contacts the landing pad,

a width of a lower portion of the landing pad is greater than a width of an upper portion of the contact plug, and

the bit line spacer contacts a side surface of each of the first to fourth insulation capping patterns of the insulation capping pattern of the bit line structure.

16. The semiconductor device of claim 15 , wherein the bit line spacer includes oxide, and/or nitride.

17. The semiconductor device of claim 15 , wherein the landing pad includes a barrier layer and a conductive layer.

18. The semiconductor device of claim 15 , wherein each of the first to fourth insulation capping patterns of the insulation capping pattern of the bit line structure includes silicon nitride.

19. The semiconductor device of claim 15 , wherein a top surface of the bit line spacer contacts the landing pad.

20. The semiconductor device of claim 15 , wherein the metal layer of the conductive line pattern of the bit line structure includes tungsten (W), and/or nitrogen (N).