Non-volatile memory with different word line hook up regions based on pass through signals

1. A non-volatile storage apparatus, comprising:

a three dimensional non-volatile memory structure that includes word lines connected to non-volatile memory cells;

one or more control circuits below the three dimensional non-volatile memory structure and configured to control the three dimensional non-volatile memory structure, the one or more control circuits include word line switch transistors, the one or more control circuits further include word line hook up signal lines connecting the word line switch transistors to word lines and pass through signal lines that provide electrical connections between components of the one or more control circuits, regions of the one or more control circuits are divided into a first set of regions and a second set of regions;

a first set of one or more metal line layers above the one or more circuits and below the three dimensional non-volatile memory structure; and

a second set of one or more metal line layers above the one or more circuits and below the three dimensional non-volatile memory structure, the first set of regions include word line hook up signal lines in the first set of one or more metal line layers and pass through signal lines in the second set of one or more metal line layers, the word line hook up signal lines are not included in the second set of one or more metal line layers in the first set of regions, the second set of regions include word line hook up signal lines in the first set of one or more metal line layers and in the second set of one or more metal line layers, the second set of regions further include pass through signal lines in the second set of one or more metal line layers.

2. The non-volatile storage apparatus of claim 1 , wherein:

the regions of the one or more control circuits that are divided into a first set of regions and a second set of regions are regions below word line hook up regions of the three dimensional non-volatile memory structure.

3. The non-volatile storage apparatus of claim 1 , wherein:

the three dimensional non-volatile memory structure includes a plurality of memory arrays, the regions of the one or more control circuits that are divided into a first set of regions and a second set of regions are regions below end portions of the memory arrays.

4. The non-volatile storage apparatus of claim 1 , wherein:

the three dimensional non-volatile memory structure includes a plurality of planes, the regions of the one or more control circuits that are divided into a first set of regions and a second set of regions are regions below and between planes.

5. The non-volatile storage apparatus of claim 1 , wherein:

in the second set of regions, the pass through signal lines are formed in the first section of each metal line layer of the second set of one or more metal line layers at a first line width and the word line hook up signal lines are formed in the second section of each metal line layer of the second set of one or more metal line layers at a second line width, the first line width is larger than the second line width.

6. The non-volatile storage apparatus of claim 1 , wherein:

in the second set of regions, the pass through signal lines are formed in the first section of each metal line layer of the second set of one or more metal line layers with a first spacing between pass through signal lines and the word line hook up signal lines are formed in the second section of each metal line layer of the second set of one or more metal line layers at a second spacing between word line hook up signal lines, the first spacing is larger than the second spacing.

7. The non-volatile storage apparatus of claim 1 , wherein:

in the second set of regions, the pass through signal lines are formed in the first section of each metal line layer of the second set of one or more metal line layers with a first ratio between signal width and spacing between signal lines and the word line hook up signal lines are formed in the second section of each metal line layer of the second set of one or more metal line layers with a second ratio between signal width and spacing between signal lines, the first ratio is different than the second ratio.

8. The non-volatile storage apparatus of claim 1 , wherein:

the first set of one or more metal line layers include multiple horizontal layers; and

the second set of one or more metal line layers include one horizontal layer above the first set of one or more metal line layers.

9. The non-volatile storage apparatus of claim 1 , further comprising:

a semiconductor die, the one or more control circuits are positioned on the semiconductor die;

the semiconductor die comprises word line switch transistor regions and sense amplifier regions;

the first set of regions are word line switch transistor regions; and

the second set of regions are word line switch transistor regions.

10. The non-volatile storage apparatus of claim 1 , further comprising:

a semiconductor die, the one or more control circuits are positioned on the semiconductor die;

the semiconductor die comprises word line switch transistor regions and sense amplifier regions;

the word line switch regions include first portions below word line hook up regions of the three dimensional non-volatile memory structure and second portions that are not below word line hook up regions of the three dimensional non-volatile memory structure;

the first set of regions are word line switch transistor regions having word line switch transistors in the first portions and not in the second portions; and

the second set of regions are word line switch transistor regions having word line switch transistors in the first portions and in the second portions, the second set of regions include horizontal word line hook up signal lines above the second portions that connect to word line switch transistors of the second portions, the first set of regions do not include horizontal word line hook up signal lines above the second portions.

11. The non-volatile storage apparatus of claim 1 , further comprising:

a memory die, the three dimensional non-volatile memory structure is part of the memory die;

a control die connected to the memory die, the one or more control circuits that are part of the control die;

the second set of regions are positioned at edges of the control die; and

the first set of regions are positioned in a middle area of the control die.

12. The non-volatile storage apparatus of claim 1 , further comprising:

a memory die, the memory die includes the three dimensional non-volatile memory structure and a first set of bond pads connected to the three dimensional non-volatile memory structure; and

a control die, the control die includes the one or more control circuits and a second set of bond pads, the first set of bond pads are connected to the second set of bond pads.

13. The non-volatile storage apparatus of claim 12 , wherein:

the word lines are arranged in an inverted staircase structure such that word line length increases from bottom to top of the three dimensional non-volatile memory structure;

the memory die includes a first metal line layer and a second metal line layer, the first metal line layer is positioned between the second metal line layer and the three dimensional non-volatile memory structure;

the three dimensional non-volatile memory structure includes bit lines formed in the first metal line layer; and

the second metal line layer includes connections from the first set of bond pads to the word lines of the inverted staircase structure.

14. The non-volatile storage apparatus of claim 13 , wherein:

the inverted staircase structure includes a first side with a first inverted staircase and a second side, opposite the first side, with a second inverted staircase; and

the first inverted staircase is wider than the second inverted staircase.

15. A non-volatile storage apparatus, comprising:

a memory die comprising multiple planes, each plane including a three dimensional non-volatile memory array, the memory die includes a first set of bond pads, each of the three dimensional non-volatile memory arrays includes bit lines and word lines connected to non-volatile memory cells; and

a control die comprising a second set of bond pads and one or more control circuits configured to control the memory die;

the one or more control circuits include word line switch transistors, word line hook up signal lines connecting the word line switch transistors with the second set of bond pads, and pass through signal lines that provide electrical connections between components of the control die;

the control die comprises a first set of one or more metal line layers and a second set of one or more metal line layers, regions of the control die below end portions of the planes of the memory die are divided into a first set of regions and a second set of regions;

the first set of regions include word line hook up signal lines in the first set of one or more metal line layers and pass through signal lines in the second set of one or more metal line layers, the word line hook up signal lines are not included in the second set of one or more metal line layers in the first set of regions;

the second set of regions include word line hook up signal lines in the first set of one or more metal line layers and in the second set of one or more metal line layers, the second set of regions further include pass through signal lines in the second set of one or more metal line layers such that the second set of one or more metal line layers include a first section for pass through signal lines and a second section for word line hook up signal lines.

16. The non-volatile storage apparatus of claim 15 , wherein:

the second set of regions are positioned at edges of the control die; and

the first set of regions are positioned in a middle area of the control die.

17. A method comprising:

fabricating a memory die comprising multiple planes, each plane including a three dimensional non-volatile memory array, the memory die includes bond pads;

fabricating a control die comprising bond pads and one or more circuits for controlling the memory die, the one or more circuits include word line switch transistors, word line hook up signal lines connecting the word line switch transistors with the bond pads, and pass through signal lines, the pass through signal lines provide electrical connections between components of the control die, the control die comprises a first set of one or more metal line layers and a second set of one or more metal line layers, regions of the control die between planes of the memory die are divided into a first set of regions and a second set of regions; and

bonding the control die to the memory die by connecting the bond pads of the memory die to the bond pads of the control die;

the fabricating the control die comprises

in the first set of regions, forming the word line hook up signal lines in the first set of one or more metal line layers and forming the pass through signal lines in the second set of one or more metal line layers, the word line hook up signal lines are not formed in the second set of one or more metal line layers in the first set of regions; and

in the second set of regions, forming the word line hook up signal lines in the first set of one or more metal line layers as well as in the second set of one or more metal line layers and forming the pass through signal lines in the second set of one or more metal line layers such that the second set of one or more metal line layers include a first section for pass through signal lines and a second section for word line hook up signal lines.

18. The method of claim 17 , wherein:

in the second set of regions, the pass through signal lines are formed in the first section of each metal line layer of the second set of one or more metal line layers at a first line width and the word line hook up signal lines are formed in the second section of each metal line layer of the second set of one or more metal line layers at a second line width, the first line width is larger than the second line width.

19. The method of claim 17 , wherein:

in the second set of regions, the pass through signal lines are formed in the first section of each metal line layer of the second set of one or more metal line layers with a first spacing between pass through signal lines and the word line hook up signal lines are formed in the second section of each metal line layer of the second set of one or more metal line layers at a second spacing between word line hook up signal lines, the first spacing is larger than the second spacing.

20. The method of claim 17 , wherein:

in the second set of regions, the pass through signal lines are formed in the first section of each metal line layer of the second set of one or more metal line layers with a first ratio between signal width and spacing between signal lines and the word line hook up signal lines are formed in the second section of each metal line layer of the second set of one or more metal line layers with a second ratio between signal width and spacing between signal lines, the first ratio is different than the second ratio.