IP Library › Granted Patent US 11,854,620
Granted Patent B2
US 11,854,620 · App. 17/351,533 · Granted Dec 26, 2023

Word line zoned adaptive initial program voltage for non-volatile memory

Inventors: Erika Penzo (San Jose, CA); Han-Ping Chen (San Jose, CA); Henry Chin (Fremont, CA)
Assignee: SanDisk Technologies LLC
G11C16/08G11C11/5628G11C11/5671G11C16/0483G11C16/10G11C16/3459H10B41/27H10B43/27
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Quick Facts
Patent No.
US 11,854,620
App. No.
17/351,533
Granted
Dec 26, 2023
Kind
B2
Abstract

An apparatus is provided that includes a plurality of word lines that include a plurality of word line zones, a plurality of non-volatile memory cells coupled to the plurality of word lines, and a control circuit coupled to the non-volatile memory cells. The control circuit is configured to determine a corresponding initial program voltage for each of the word line zones. Each corresponding initial program voltage is determined based on a number of program erase cycles.

Claims (33)

1. An apparatus comprising:

a plurality of word lines comprising a plurality of word line zones;

a plurality of non-volatile memory cells coupled to the plurality of word lines; and

a control circuit coupled to the non-volatile memory cells, the control circuit configured to determine a corresponding initial program voltage for each of the word line zones, wherein each corresponding initial program voltage is determined based on a number of program erase cycles,

wherein for each word line zone, the control circuit is configured to determine the corresponding initial program voltage based on an average increase of a programmed state threshold voltage position across word lines in the word line zone.

2. The apparatus of claim 1 , wherein the programmed state is a lowest programmed state.

3. The apparatus of claim 1 , wherein for each word line zone, the control circuit is configured to determine the corresponding initial program voltage based on an average increase of a lower tail of a programmed state threshold voltage distribution.

4. The apparatus of claim 3 , wherein the programmed state is a first programmed state above an erased state.

5. The apparatus of claim 1 , wherein each word line zone includes consecutive word lines.

6. The apparatus of claim 1 , wherein each word line zone includes a same number of word lines.

7. The apparatus of claim 1 , wherein a number of word lines in each word line zone varies from word line zone to word line zone.

8. The apparatus of claim 1 , wherein the word line zones are non-overlapping.

9. The apparatus of claim 1 , wherein each word line is included in at most one word line zone.

10. An apparatus comprising:

a plurality of word lines comprising a plurality of word line zones;

a plurality of non-volatile memory cells coupled to the plurality of word lines; and

a control circuit coupled to the non-volatile memory cells, the control circuit configured to determine a first initial program voltage for non-volatile memory cells coupled to a first word line, and a second initial program voltage for non-volatile memory cells coupled to a second word line, wherein the first initial program voltage and the second initial program voltage vary based on a number of program erase cycles,

wherein the control circuit is further configured to determine the first initial program voltage based on an average increase of a lower tail of a programmed state threshold voltage distribution for memory cells coupled to the first word line, and determine the second initial program voltage based on an average increase of a lower tail of the programmed state threshold voltage distribution for memory cells coupled to the second word line.

11. The apparatus of claim 10 , wherein the first initial program voltage differs from the second initial program voltage.

12. The apparatus of claim 10 , wherein the control circuit is further configured to determine the first initial program voltage based on an average increase of a programmed state threshold voltage position of non-volatile memory cells coupled to the first word line, and determine the second initial program voltage based on an average increase of the programmed state threshold voltage position of non-volatile memory cells coupled to the second word line.

13. The apparatus of claim 12 , wherein the programmed state is a lowest programmed state.

14. The apparatus of claim 10 , wherein the programmed state is a first programmed state above an erased state.

15. The apparatus of claim 10 , further comprising a first word line zone that comprises the first word line, and a second word line zone that comprises the second word line.

16. The apparatus of claim 10 , wherein the first word line zone includes a first number of word lines, and the second word line zone includes a second number of word lines different from the first number of word lines.

17. A method comprising:

dividing a first plurality of word lines into a first word line zone and a second plurality of word lines into a second word line zone;

determining an average increase of a programmed state threshold voltage position in the first word line zone;

determining an average increase of a programmed state threshold voltage position in the second word line zone;

determining a first initial program voltage for the first word line zone based on a number of program erase cycles and the determined average increase of a programmed state threshold voltage position in the first word line zone;

determining a first initial program voltage for the first word line zone based on the number of program erase cycles and the determined average increase of a programmed state threshold voltage position in the second word line zone;

applying a single program pulse comprising the first initial program voltage to program non-volatile memory cells coupled to the first plurality of word lines to a programmed state without performing any verify operations; and

applying a single program pulse comprising the second initial program voltage to program non-volatile memory cells coupled to the second plurality of word lines to the programmed state without performing any verify operations.

18. The method of claim 17 , wherein first initial program voltage differs from the second initial program voltage.

Assignments (4)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2024
From: SANDISK TECHNOLOGIES LLC
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 069796/0423 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 18, 2021
From: PENZO, ERIKA; CHEN, HAN-PING; CHIN, HENRY
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 056585/0680 →
Continuity (1)
Related Publication 20220406380A1 · Dec 22, 2022
Cited By (2)
US 12,230,344 US 12,354,680