Three-dimensional memory device including low-k drain-select-level isolation structures and methods of forming the same
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory opening fill structures located within an array of memory openings vertically extending through the alternating stack, and a drain-select-level isolation structure vertically extending through drain-select-level electrically conductive layers between two rows of memory opening fill structures. The drain-select-level isolation structure may comprise a low-k dielectric material or an air gap.
1. A three-dimensional memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate, wherein the electrically conductive layers comprise word-line-level electrically conductive layers and drain-select-level electrically conductive layers overlying the word-line-level electrically conductive layers;
an array of memory opening fill structures located within an array of memory openings vertically extending through the alternating stack; and
a drain-select-level isolation structure vertically extending through the drain-select-level electrically conductive layers between two rows of memory opening fill structures of the array of memory opening structures and laterally extending along a first horizontal direction, and comprising a dielectric liner, a dielectric fill material portion contained within the dielectric liner, and an air gap.
2. The three-dimensional memory device of claim 1 , wherein each of the memory opening fill structures comprises a respective vertical semiconductor channel, a respective memory film, and a respective drain region contacting a top end of the respective vertical semiconductor channel.
3. The three-dimensional memory device of claim 2 , further comprising:
a contact-level dielectric layer overlying the alternating stack and the array of memory opening fill structures; and
drain contact via structures vertically extending through the contact-level dielectric layer and contacting a top surface of a respective one of the drain regions.
4. The three-dimensional memory array of claim 3 , further comprising:
a first backside trench fill structure laterally extending along the first horizontal direction and contacting first sidewalls of each layer within the alternating stack; and
a second backside trench fill structure laterally extending along the first horizontal direction and laterally spaced from the first backside trench fill structure and contacting second sidewalls of each layer within the alternating stack,
wherein top surfaces of the first backside trench fill structure and the second backside trench fill structure are located within a horizontal plane including a top surface of the contact-level dielectric layer.
5. The three-dimensional memory device of claim 4 , wherein the drain contact via structures protrude above the horizontal plane including the top surface of the contact-level dielectric layer.
6. The three-dimensional memory device of claim 3 , further comprising a capping dielectric material layer comprising a horizontally-extending portion that overlies the top surface of the contact-level dielectric layer, wherein the dielectric fill material portion comprises a vertically-extending portion of the capping dielectric material layer.
7. The three-dimensional memory device of claim 6 , wherein top surfaces of the drain contact via structures are located below a horizontal plane including a top surface of the capping dielectric material layer.
8. The three-dimensional memory device of claim 6 , wherein the air gap comprises an additional volume embedded within the horizontally-extending portion of the capping dielectric material layer and connected to the volume of the air gap within the drain-select-level isolation structure.
9. The three-dimensional memory device of claim 6 , further comprising a hard mask dielectric layer located between the contact-level dielectric layer and the capping dielectric material layer, wherein the dielectric liner contacts a sidewall of the hard mask dielectric layer.
10. The three-dimensional memory device of claim 9 , wherein the capping dielectric material layer contacts a top surface of the hard mask dielectric layer.
11. The three-dimensional memory device of claim 6 , wherein the dielectric liner comprises a top surface contacting a bottom surface of the horizontally-extending portion of the capping dielectric material layer.
12. The three-dimensional memory device of claim 1 , wherein the air gap is laterally surrounded by the dielectric fill material portion, and is spaced from the dielectric liner by the dielectric fill material portion.
13. The three-dimensional memory device of claim 1 , wherein the air gap underlies the dielectric fill material portion and comprises a boundary that coincides within an inner sidewall of the dielectric liner.
14. The three-dimensional memory device of claim 1 , wherein the memory opening fill structures within the two rows of memory opening fill structures comprise a respective planar straight sidewall in contact with a respective portion of a pair of straight sidewalls of the drain-select-level isolation structure.