Systems and methods of reducing detection error and duty error in memory devices
Systems and methods are provided that combine a write duty cycle adjuster with write training to reduce detection and duty cycle errors in memory devices. Various embodiments herein perform write duty cycle adjuster operations to adjust a duty cycle of a clock signal that coordinates a data signal with a data operation on the memory device based on an error in the duty cycle, and performs write training operations to detect a skew between the data signal and the clock signal and adjust a sampling transition of the duty cycle of the clock signal to align with a valid data window of the data signal.
1. A method comprising: detecting a change to one or more of a process, voltage, or temperature (PVT) of a memory device; adjusting a data strobe by adjusting a duty cycle of the data strobe that coordinates a data operation with the memory device based on detection of a change of a duty cycle for the data strobe; monitoring at least one data eye of a data signal to determine whether a comparison between a first portion of the data signal and a second portion of the data signal meets a first threshold value, wherein the adjusted data strobe comprises a first strobe for placement in the first portion and a second strobe for placement in the second portion; and adjusting an aspect of one or more of the adjusted data strobe and the data signal based on a determination that the comparison does not meet the first threshold value.
2. The method of claim 1 , further comprising monitoring the duty cycle of the data strobe based on the detected change to one or more of the PVT that exceeds a second threshold.
3. The method of claim 1 , wherein monitoring at least one data eye of a data signal to determine whether a comparison between a first portion of the data signal and a second portion of the data signal meets a first threshold value comprises comparing an overlap of a first block of the first portion and a second block of the second portion to the first threshold value to determine that the overlap meets a threshold amount requirement.
4. The method of claim 3 , wherein adjusting an aspect of the data strobe or the data signal based on a determination that the comparison does not meet the first threshold value comprises shifting one or more of the first strobe and the second strobe to the left or right with respect to time relative to one or more of the first portion and the second portion, respectively, when the overlap is less than the threshold amount requirement.
5. The method of claim 1 , wherein monitoring at least one data eye of a data signal to determine whether a comparison between a first portion of the data signal and a second portion of the data signal meets a second threshold value comprises comparing a first length of a first block of the first portion and a second length of a second block of the second portion to determine that a difference between the first and second lengths is less than a threshold length.
6. The method of claim 5 , wherein adjusting an aspect of the data strobe or the data signal based on a determination that the comparison does not meet the second threshold value comprises increasing a first duty cycle of the first portion and decreasing a second duty cycle of the second portion or decreasing the first duty cycle and increasing the second duty cycle when the difference between the first and second lengths is greater than the threshold length.
7. The method of claim 1 , wherein adjusting the duty cycle of the data strobe comprises increasing the duty cycle or decreasing the duty cycle.
8. A controller, comprising: a processor; and a memory configured to store instructions that, when executed by the processor in accordance with a clocking signal, cause the processor to: detect a change to one or more of a process, voltage, or temperature (PVT) of a memory device; adjust a data strobe by adjusting the duty cycle of the data strobe that coordinates a data operation with the memory device based on detection of a change of a duty cycle for the data strobe; monitor at least one data eye of a data signal to determine whether a comparison between a first portion of the data signal and a second portion of the data signal meets a first threshold value, wherein the adjusted data strobe comprises a first strobe for placement in the first portion and a second strobe for placement in the second portion; and adjusting an aspect of one or more of the adjusted data strobe and the data signal based on a determination that the comparison does not meet the first threshold value.
9. The controller of claim 8 , wherein the instructions further cause the processor to monitor the duty cycle of the data strobe based on the detected change to one or more of the PVT that exceeds a second threshold.
10. The controller of claim 9 , wherein the instructions that cause the processor to monitor at least one data eye of a data signal to determine whether a comparison between a first portion of the data signal and a second portion of the data signal meets a first threshold value comprise instructions that cause the processor to compare an overlap of a first block of the first portion and a second block of the second portion to the first threshold value to determine that the overlap meets a threshold amount requirement.
11. The controller of claim 10 , wherein the instructions that cause the processor to adjust an aspect of the data strobe or the data signal based on a determination that the comparison does not meet the first threshold value comprise instructions that cause the processor to shift one or more of the first strobe and the second strobe to the left or right with respect to time relative to one or more of the first portion and the second portion, respectively, when the overlap is less than the threshold amount requirement.
12. The controller of claim 8 , wherein the instructions that cause the processor to monitor at least one data eye of a data signal to determine whether a comparison between a first portion of the data signal and a second portion of the data signal meets a second threshold value comprise instructions that cause the processor to compare a first length of a first block of the first portion and a second length of a second block of the second portion to determine that a difference between the first and second lengths is less than a threshold length.
13. The controller of claim 12 , wherein the instructions that cause the processor to adjust an aspect of the data strobe or the data signal based on a determination that the comparison does not meet the second threshold value comprise instructions that cause the processor to increase a first duty cycle of the first portion and decreasing a second duty cycle of the second portion or decreasing the first duty cycle and increasing the second duty cycle when the difference between the first and second lengths is greater than the threshold length.
14. The controller of claim 8 , wherein the instructions that cause the processor to adjust the duty cycle of the data strobe comprise instructions that cause the processor to increase the duty cycle or decreasing the duty cycle.
15. The controller of claim 8 , wherein the memory and the processor are mounted to a memory die.