Transistor and semiconductor device
A transistor with small parasitic capacitance can be provided. A transistor with high frequency characteristics can be provided. A semiconductor device including the transistor can be provided. Provided is a transistor including an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor has a first region where the first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween; a second region where the first conductor overlaps with the second conductor with the first and second insulators positioned therebetween; and a third region where the first conductor overlaps with the third conductor with the first and second insulators positioned therebetween. The oxide semiconductor including a fourth region where the oxide semiconductor is in contact with the second conductor; and a fifth region where the oxide semiconductor is in contact with the third conductor.
1. A semiconductor device comprising:
a first transistor; and
a second transistor over the first transistor, the second transistor electrically connected to the first transistor,
wherein the first transistor comprises silicon in a channel formation region,
wherein the second transistor comprises:
a first insulating layer over the first transistor;
an oxide semiconductor layer over the first insulating layer;
a second insulating layer over the oxide semiconductor layer, the second insulating layer having an opening;
a gate electrode, a first part of the gate electrode provided in the opening; and
a gate insulating layer provided between the oxide semiconductor layer and the gate electrode,
wherein the first insulating layer comprises a first region overlapped with the oxide semiconductor layer and a second region not overlapped with the oxide semiconductor layer,
wherein a thickness of the first region of the first insulating layer is larger than a thickness of the second region of the first insulating layer,
wherein, in a cross section parallel to a channel width direction of the second transistor, a second part of the gate electrode does not overlap with the oxide semiconductor layer, and
wherein, in the cross section parallel to the channel width direction of the second transistor, a bottom surface of the second part of the gate electrode is located below a bottom surface of the oxide semiconductor layer.
2. The semiconductor device according to claim 1 , wherein the channel formation region of the first transistor is provided in a silicon substrate.
3. The semiconductor device according to claim 1 , wherein the channel formation region of the first transistor is provided in a silicon layer formed on an insulating surface.
4. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer includes a channel formation region of the second transistor.
5. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer comprises indium and zinc.
6. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer comprises indium, gallium, and zinc.
7. A semiconductor device comprising:
a first transistor; and
a second transistor over the first transistor, the second transistor electrically connected to the first transistor,
wherein the first transistor comprises silicon in a channel formation region,
wherein the second transistor comprises:
a first insulating layer over the first transistor;
a first oxide semiconductor layer over the first insulating layer;
a second oxide semiconductor layer over the first oxide semiconductor layer;
a second insulating layer over the second oxide semiconductor layer, the second insulating layer comprising an opening;
a gate electrode, a first part of the gate electrode provided in the opening; and
a gate insulating layer located between the second oxide semiconductor layer and the gate electrode,
wherein the first insulating layer comprises a first region overlapped with the first oxide semiconductor layer and a second region not overlapped with the first oxide semiconductor layer,
wherein a thickness of the first region of the first insulating layer is larger than a thickness of the second region of the first insulating layer,
wherein, in a cross section parallel to a channel width direction of the second transistor, a second part of the gate electrode does not overlap with the first oxide semiconductor layer and the second oxide semiconductor layer, and
wherein, in the cross section parallel to the channel width direction of the second transistor, a bottom surface of the second part of the gate electrode is located below a bottom surface of the first oxide semiconductor layer.
8. The semiconductor device according to claim 7 , wherein the channel formation region of the first transistor is provided in a silicon substrate.
9. The semiconductor device according to claim 7 , wherein the channel formation region of the first transistor is provided in a silicon layer formed on an insulating surface.
10. The semiconductor device according to claim 7 , wherein at least the second oxide semiconductor layer includes a channel formation region of the second transistor.
11. The semiconductor device according to claim 7 , wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises indium and zinc.
12. The semiconductor device according to claim 7 , wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises indium, gallium, and zinc.
13. A semiconductor device comprising:
a first transistor; and
a second transistor over the first transistor, the second transistor electrically connected to the first transistor,
wherein the first transistor comprises silicon in a channel formation region,
wherein the second transistor comprises:
a first insulating layer;
a first oxide semiconductor layer over the first insulating layer;
a second oxide semiconductor layer over the first oxide semiconductor layer;
a second insulating layer over the second oxide semiconductor layer, the second insulating layer comprising an opening;
a gate electrode, a first part of the gate electrode provided in the opening;
a gate insulating layer located between the second oxide semiconductor layer and the gate electrode; and
a third oxide semiconductor layer located between the second oxide semiconductor layer and the gate insulating layer,
wherein the first insulating layer comprises a first region overlapped with the first oxide semiconductor layer and a second region not overlapped with the first oxide semiconductor layer,
wherein a thickness of the first region of the first insulating layer is larger than a thickness of the second region of the first insulating layer,
wherein, in a cross section parallel to a channel width direction of the second transistor, a second part of the gate electrode does not overlap with the first oxide semiconductor layer and the second oxide semiconductor layer, and
wherein, in the cross section parallel to the channel width direction of the second transistor, a bottom surface of the second part of the gate electrode is located below a bottom surface of the first oxide semiconductor layer.
14. The semiconductor device according to claim 13 , wherein the channel formation region of the first transistor is provided in a silicon substrate.
15. The semiconductor device according to claim 13 , wherein the channel formation region of the first transistor is provided in a silicon layer formed on an insulating surface.
16. The semiconductor device according to claim 13 , wherein at least the second oxide semiconductor layer includes a channel formation region of the second transistor.
17. The semiconductor device according to claim 13 , wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises indium and zinc.
18. The semiconductor device according to claim 13 , wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises indium, gallium, and zinc.