Diffusion barrier layer for source and drain structures to increase transistor performance

1. A semiconductor device, comprising:

a gate electrode overlying a semiconductor substrate;

an epitaxial source/drain layer disposed on the semiconductor substrate and laterally adjacent to the gate electrode, wherein the epitaxial source/drain layer comprises a first dopant; and

a diffusion barrier layer between the epitaxial source/drain layer and the semiconductor substrate, wherein the diffusion barrier layer is co-doped with the first dopant and a barrier dopant that is different from the first dopant, wherein a doping concentration of the barrier dopant within the diffusion barrier layer is less than a doping concentration of the first dopant within the diffusion barrier layer, wherein a doping profile of the barrier dopant in the diffusion barrier layer comprises a gaussian distribution.

2. The semiconductor device of claim 1 , wherein a doping concentration of the first dopant within the epitaxial source/drain layer is greater than the doping concentration of the first dopant within the diffusion barrier layer.

3. The semiconductor device of claim 1 , wherein the barrier dopant is configured to prevent diffusion of the first dopant from the epitaxial source/drain layer to a region of the semiconductor substrate directly underlying the gate electrode.

4. The semiconductor device of claim 1 , wherein the diffusion barrier layer comprises epitaxial silicon, and a thickness of the epitaxial source/drain layer is greater than a thickness of the diffusion barrier layer.

5. The semiconductor device of claim 1 , wherein a bottom surface of the diffusion barrier layer is disposed below a top surface of the semiconductor substrate, and wherein a bottom surface of the epitaxial source/drain layer is vertically above the top surface of the semiconductor substrate.

6. The semiconductor device of claim 1 , wherein the diffusion barrier layer consists essentially of silicon, carbon, and phosphorus (SiCP), and the epitaxial source/drain layer consists essentially of silicon and phosphorus (SiP).

7. The semiconductor device of claim 1 , wherein the diffusion barrier layer consists essentially of silicon, carbon, and arsenic (SiCAs), and the epitaxial source/drain layer consists essentially of silicon and arsenic (SiAs).

8. The semiconductor device of claim 1 , wherein the diffusion barrier layer is a doped region of the semiconductor substrate extending from a top surface of the semiconductor substrate to a point below the top surface of the semiconductor substrate, wherein the epitaxial source/drain layer is disposed along a top surface of the diffusion barrier layer.

9. An integrated chip, comprising:

a semiconductor-on-insulator (SOI) substrate comprising a first semiconductor layer, a second semiconductor layer, and an insulating layer disposed between the first and second semiconductor layers;

an N-type metal oxide semiconductor (NMOS) transistor disposed over the first semiconductor layer, wherein the NMOS transistor comprises a gate electrode, a gate dielectric layer disposed between the gate electrode and the first semiconductor layer, and a pair of source/drain structures disposed on opposing sides of the gate electrode, wherein the pair of source/drain structures comprise:

a first pair of epitaxial source/drain layers over the first semiconductor layer, wherein the first pair of source/drain epitaxial layers comprise a first N-type dopant; and

diffusion barrier layers disposed between the first semiconductor layer and the first pair of source/drain epitaxial layers, wherein the diffusion barrier layers comprise a barrier dopant that is different from the first N-type dopant, wherein the diffusion barrier layers extend continuously from a top surface of the first semiconductor layer to a top surface of the insulating layer.

10. The integrated chip of claim 9 , wherein the diffusion barrier layers comprise a first atomic percentage of the first N-type dopant and a second atomic percentage of the barrier dopant, wherein the first atomic percentage is no less than the second atomic percentage.

11. The integrated chip of claim 9 , wherein the diffusion barrier layers are epitaxial layers co-doped with a second N-type dopant and the barrier dopant, wherein the first N-type dopant is different from the second N-type dopant.

12. The integrated chip of claim 11 , wherein the first N-type dopant comprises phosphorous and the second N-type dopant comprises arsenic.

13. The integrated chip of claim 9 , further comprising:

a P-type metal oxide semiconductor (PMOS) transistor disposed over the first semiconductor layer and laterally adjacent to the NMOS transistor, wherein the PMOS transistor comprises a second gate electrode, a second gate dielectric layer underlying the second gate electrode, and a second pair of epitaxial source/drain layers disposed on opposing sides of the second gate electrode, wherein a bottom surface of the second pair of epitaxial source/drain layers is aligned with a bottom surface of the diffusion barrier layers.

14. The integrated chip of claim 9 , wherein the first pair of source/drain epitaxial layers and the diffusion barrier layers have a trapezoidal shape.

15. An integrated chip, comprising:

a gate structure overlying a semiconductor substrate;

a source/drain layer disposed on the semiconductor substrate and adjacent a side of the gate structure, wherein the source/drain layer comprises a first dopant; and

a diffusion barrier layer between the source/drain layer and the semiconductor substrate, wherein the diffusion barrier layer comprises a second dopant different from the first dopant, wherein a doping concentration of the second dopant within the diffusion barrier layer is less than a doping concentration of the first dopant within the source/drain layer, and wherein a thickness of the diffusion barrier layer is less than a thickness of the source/drain layer, wherein a region of the semiconductor substrate directly contacting a bottom surface of the diffusion barrier layer has a doping type opposite the first dopant.

16. The integrated chip of claim 15 , wherein the semiconductor substrate comprises a fin structure under the gate structure, wherein the diffusion barrier layer is disposed along a sidewall of the fin structure.

17. The integrated chip of claim 15 , wherein the diffusion barrier layer is disposed within the semiconductor substrate, wherein the bottom surface of the diffusion barrier layer is disposed below a bottom surface of the gate structure.

18. The integrated chip of claim 15 , wherein the diffusion barrier layer comprises the first dopant.

19. The integrated chip of claim 15 , further comprising:

a P-type metal oxide semiconductor (PMOS) transistor disposed over the semiconductor substrate, wherein the PMOS transistor comprises a second gate structure and a second source/drain layer adjacent to a side of the second gate structure, wherein a bottom surface of the second source/drain layer is aligned with the bottom surface of the diffusion barrier layer.

20. The integrated chip of claim 19 , wherein a thickness of the second source/drain layer is greater than the thickness of the source/drain layer.