Semiconductor device and method
View Patent ↗An embodiment includes a device including a first fin extending from a substrate. The device also includes a first gate stack over and along sidewalls of the first fin. The device also includes a first gate spacer disposed along a sidewall of the first gate stack. The device also includes a first source/drain region in the first fin and adjacent the first gate spacer, the first source/drain region including a first carbon-containing buffer layer on the first fin. The device also includes and a first epitaxial structure on the first carbon-containing buffer layer.
1 . A method comprising:
depositing a first dummy gate over and along sidewalls of a first fin extending upwards from a substrate;
forming a first gate spacer along a sidewall of the first dummy gate;
forming a first recess in the first fin adjacent the first gate spacer; and
forming a first source/drain region in the first recess, the forming the first source/drain region comprising:
epitaxially growing a first carbon-containing buffer layer in the first recess, the first carbon-containing buffer layer being thicker at a bottom than at sides of the first source/drain region; and
epitaxially growing a first doped layer from the first carbon-containing buffer layer in the first recess, the first doped layer being over the first carbon-containing buffer layer, the first carbon-containing buffer layer comprising silicon arsenide doped with carbon, and the first doped layer comprising silicon carbide, wherein the first carbon-containing buffer layer and the first doped layer are epitaxially grown in a single continuous process with changing gas flows of precursors, wherein the first recess has a depth D 1 in a range from 35 nm to 60 nm as measured from a top surface of the first fin, and wherein the first carbon-containing buffer layer has a first thickness in a range from 1 to 6 nm on the side of the first recess measured at a depth of ½ D 1 .
2 . The method of claim 1 , wherein the first carbon-containing buffer layer has a weight percentage (wt %) of carbon in a range from 0.2 wt % to 2.0 wt %.
3 . The method of claim 1 further comprising:
replacing the first dummy gate with a functional gate stack disposed over and along sidewalls of the first fin.
4 . The method of claim 1 , wherein the first doped layer has a faceted top surface raised above an upper surface of the first fin.
5 . The method of claim 1 , wherein the first carbon-containing buffer layer has a thickness in a range from 1 nm to 6 nm on a sidewall of the first source/drain region.
6 . The method of claim 1 , wherein epitaxially growing the first carbon-containing buffer layer comprises:
epitaxially growing the first carbon-containing buffer layer at a first temperature and with a first set of precursors, the first temperature being in a range from 600° C. to 800° C., the first set of precursors including a carbon precursor, a silicon precursor, and an arsenic precursor, the carbon precursor comprising trimethylsilane, the silicon precursors comprising trichlorosilane (TCS), dichlorosilane (DCS), SiH 4 , Si 2 H 6 , Si 3 H 8 , or a combination thereof, and the arsenic precursor comprising AsH 3 .
7 . The method of claim 1 further comprising:
depositing a second dummy gate over and along sidewalls of a second fin extending upwards from the substrate;
forming a second gate spacer along a sidewall of the second dummy gate;
forming a second recess in the second fin adjacent the second gate spacer; and
forming a second source/drain region in the first recess, the forming the second source/drain region comprising:
epitaxially growing a second carbon-containing buffer layer in the first recess, the first carbon-containing buffer layer being thicker at a bottom than at sides of the first source/drain region; and
epitaxially growing a second doped layer from the second carbon-containing buffer layer in the first recess, the second doped layer being over the second carbon-containing buffer layer, the second carbon-containing buffer layer comprising silicon boron doped with carbon, and the first doped layer comprising germanium.
8 . The method of claim 1 , wherein the first carbon-containing buffer layer has an arsenic concentration in a range from 2×10 20 cm −3 to 2×10 21 cm −3 .
9 . A method comprising:
forming a first dummy gate over and along sidewalls of a first fin extending upwards from a substrate;
forming a second dummy gate over and along sidewalls of a second fin extending upwards from the substrate;
forming a first gate spacer along a sidewall of the first dummy gate;
forming a second gate spacer along a sidewall of the second dummy gate;
etching a first recess in the first fin adjacent the first gate spacer;
etching a second recess in the second fin adjacent the second gate spacer;
forming a first source/drain region in the first recess, the first source/drain region comprising a first buffer layer and a first epitaxial structure, the first buffer layer comprising carbon, the first buffer layer being grown from the first fin in the first recess, the first buffer layer being thicker at a bottom than at sides of the first recess, the first epitaxial structure being grown from the first buffer layer, the first epitaxial structure comprising silicon and phosphorus, wherein forming the first buffer layer comprises:
epitaxially growing the first buffer layer at a first temperature and with a first set of precursors, the first temperature being in a range from 600° C. to 800° C., the first set of precursors including a carbon precursor, a silicon precursor, and an arsenic precursor, the carbon precursor comprising trimethylsilane, the silicon precursors comprising trichlorosilane (TCS), dichlorosilane (DCS), SiH 4 , Si 2 H 6 , Si 3 H 8 , or a combination thereof, and the arsenic precursor comprising AsH 3 , wherein the first buffer layer comprises silicon arsenide doped with carbon having an arsenic concentration in a range from 2×10 20 cm −3 to 2×10 21 cm −3 , and the first epitaxial structure has an impurity concentration in a range from 5×10 20 cm −3 to 5×10 21 cm −3 ;
forming a second source/drain region in the second recess, the second source/drain region comprising a second epitaxial structure, the second epitaxial structure comprising silicon and boron, the second source/drain region being free from a carbon-containing buffer layer;
replacing the first dummy gate with a first functional gate stack disposed over and along sidewalls of the first fin; and
replacing the second dummy gate with a second functional gate stack disposed over and along sidewalls of the second fin.
10 . The method of claim 9 , wherein the first epitaxial structure has a faceted top surface.
11 . The method of claim 9 further comprising:
forming an etch stop layer over the first source/drain region and on a sidewall of the first gate spacer;
forming a first interlayer dielectric over the etch stop layer;
forming a second interlayer dielectric over the first interlayer dielectric;
etching a hole through the first and second interlayer dielectrics and the etch stop layer; and
forming a first conductive contact in the hole, the first conductive contact being electrically coupled to the first source/drain region.
12 . The method of claim 9 , wherein the first buffer layer comprises silicon arsenide doped with carbon, and wherein the first buffer layer has a weight percentage (wt %) of carbon in a range from 0.2 wt % to 2.0 wt %.
13 . A method comprising:
forming a first fin and a second fin over a substrate, the fins extending over a major surface of the substrate;
forming a first gate stack over and along sidewalls of the first fin;
forming a second gate stack over and along sidewalls of the second fin;
forming a first gate spacer along a sidewall of the first gate stack;
forming a second gate spacer along a sidewall of the second gate stack;
etching a first recess in the first fin and a second recess in the second fin, bottom surfaces of the first and second recesses being separated from the major surface of the substrate;
forming a first source/drain region in the first fin and a second source/drain region in the second fin, the first source/drain region being adjacent the first gate spacer, the second source/drain region being adjacent the second gate spacer, wherein forming the first source/drain region and the second source/drain region comprises:
forming a first carbon-containing buffer layer in the first recess in the first fin, the first carbon-containing buffer layer being thicker at a bottom than at sides of the first recess, the first carbon-containing buffer layer comprising silicon arsenide doped with carbon;
forming a second carbon-containing buffer layer in the second recess in the second fin, the second carbon-containing buffer layer being thicker at a bottom than at sides of the second recess, the second carbon-containing buffer layer comprising silicon boron doped with carbon;
forming a first epitaxial structure on the first carbon-containing buffer layer; and
forming a second epitaxial structure on the second carbon-containing buffer layer, wherein the first recess has a depth D 1 in a range from 35 nm to 60 nm as measured from a top surface of the first fin, and wherein the first carbon-containing buffer layer has a first thickness on the side of the first recess measured at a depth of ½ D 1 , the first thickness being in a range from 1 nm to 6 nm.
14 . The method of claim 13 , wherein the first epitaxial structure has a faceted top surface.
15 . The method of claim 13 wherein the first carbon-containing buffer layer has a weight percentage (wt %) of carbon in a range from 0.2 wt % to 2.0 wt %.
16 . The method of claim 13 further comprising:
forming an etch stop layer over the first source/drain region and on a sidewall of the first gate spacer;
forming a first interlayer dielectric over the etch stop layer;
forming a second interlayer dielectric over the first interlayer dielectric; and
forming a first conductive contact extending through the first and second interlayer dielectrics and the etch stop layer, the first conductive contact being electrically coupled to the first source/drain region.
17 . The method of claim 16 , wherein the first conductive contact physically contacts the first epitaxial structure, and the first conductive contact is separated from the first carbon-containing buffer layer by the first epitaxial structure.
18 . The method of claim 13 , wherein the first epitaxial structure contacts the first gate spacer.
19 . The method of claim 13 , wherein the first epitaxial structure comprises silicon, silicon carbide, phosphorous doped silicon carbide, or silicon phosphide.
20 . The method of claim 13 , wherein the first epitaxial structure comprises silicon carbide.