Semiconductor device and method for fabricating the same
A semiconductor device includes a gate structure on a substrate, an offset spacer adjacent to the gate structure, a main spacer around the offset spacer, a source/drain region adjacent to two sides of the main spacer, a contact etch stop layer (CESL) adjacent to the main spacer, and an interlayer dielectric (ILD) layer around the CESL. Preferably, a dielectric constant of the offset spacer is higher than a dielectric constant of the main spacer.
1. A semiconductor device, comprising:
a gate structure on a substrate;
a spacer adjacent to and in direct contact with the gate structure, wherein the spacer comprises only a single layer, a dielectric constant of the spacer proximate to the gate structure is higher than a dielectric constant of the spacer away from the gate structure; and
a source/drain region adjacent to two sides of the spacer.
2. The semiconductor device of claim 1 , wherein an oxygen concentration in the spacer increases in a direction away from the gate structure.
3. The semiconductor device of claim 2 , wherein the spacer proximate to the gate is SiCN and the spacer away from the gate is SiOCN.
4. The semiconductor device of claim 3 , wherein the gate structure is a metal gate.
5. The semiconductor device of claim 4 , wherein an epitaxial layer source/drain region is formed in a fin-shaped structure adjacent to two sides of the spacer.
6. The semiconductor of claim 1 , further comprising:
a contact etch stop layer (CESL) adjacent to the main spacer; and
an interlayer dielectric (ILD) layer around the CESL.
7. The semiconductor device of claim 6 , wherein an oxygen concentration in the ILD layer is greater than an oxygen concentration in the CESL.
8. The semiconductor device of claim 7 , wherein an oxygen concentration on a surface of the CESL is greater than an oxygen concentration inside the CESL.
9. The semiconductor device of claim 7 , wherein a dielectric constant of the spacer is higher than a dielectric constant of the CESL.