Stacked devices and methods of fabrication
Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.
1. A method of making a bonded image sensor device, comprising:
creating conductive through-vias in a carrier wafer;
hybrid bonding a first element to the carrier wafer, including conductively bonding first contacts of the first element to face and conductively connect to first ends of the conductive through-vias in the carrier wafer, wherein the first element has a first footprint size;
hybrid bonding a second element to the carrier wafer, including conductively bonding second contacts of the second element to face and conductively connect to second ends of the conductive through-vias of the carrier wafer, wherein the second element has a second footprint size different from the first footprint size; and
at least partly filling lateral spaces around the second element with an encapsulating material, wherein one of the first element or the second element is an image sensor and the other of the first element or the second element is an image processor.
2. The method of claim 1 , wherein the encapsulating material comprises a material selected from the group consisting of a resist compound, silicon, a high thermal conductivity compound, diamond, and aluminum nitride.
3. The method of claim 1 , wherein:
the first element comprises the image sensor and is located on a first side of the carrier wafer and the second element comprises the image processor and is located on a second side of the carrier wafer; and
the image sensor and the image processor are of different process technologies, different form factors, or different nodes.
4. The method of claim 1 , wherein:
the first element comprises a first wafer comprising multiple image sensor dies, the image sensor dies having a third footprint size; and
the second element comprises a logic die from a second wafer, the second wafer having a fourth footprint size different from the first footprint size.
5. The method of claim 4 , wherein the second footprint size is different from third footprint size.
6. The method of claim 1 , wherein the encapsulating material is selected from the group consisting of a glass, a silicon spacer material, or a thermally conductive compound.
7. The method of claim 1 , further comprising simultaneous polishing of the encapsulating material and the second element.
8. The method of claim 7 , wherein the polishing comprises chemical mechanical planarization.
9. The method of claim 1 , wherein the first element comprises an image sensor, further comprising:
processing a backside of the image sensor after conductively bonding the first element; and
opening contacts to the image sensor.
10. The method of claim 9 , wherein opening contacts to the image sensor is conducted after processing the backside.
11. The method of claim 1 , further comprising providing bond pads over the first ends and/or the second ends of the conductive through-vias in the carrier wafer.
12. The method of claim 11 , wherein providing the bond pads comprises providing a hybrid bonding layer.
13. A method of making a bonded image sensor device, comprising:
creating conductive through-vias in a carrier wafer;
conductively bonding a first element to first ends of the conductive through-vias in the carrier wafer, wherein the first element has a first footprint size;
conductively bonding a second element to second ends of the conductive through-vias of the carrier wafer, wherein the second element has a second footprint size different from the first footprint size; and
at least partly filling lateral spaces around the second element with an encapsulating material, wherein one of the first element or the second element is an image sensor and the other of the first element or the second element is an image processor;
planarizing a surface of the second element; and
planarizing a surface of the encapsulating material.
14. The method of claim 13 , wherein the surface of the second element comprises a back surface of the logic die.
15. The method of claim 14 , further comprising:
direct-bonding a third element to the top surface of the first element.
16. The method of claim 15 , further comprising:
at least partially filling-in space around the third element.
17. The method of claim 16 , further comprising:
direct bonding a fourth element on a second element, wherein the second, third and fourth elements comprise dies; and
at least partially filling in space around the fourth element.
18. The method of claim 15 , wherein the direct-bonding between the first element and the third element comprises direct hybrid bonding of conductive interconnects between the first element and the third element.