Thin film semiconductor switching device
Novel semiconductor devices are taught. The novel devices include a thin film transistor (TFT) with an n-type semiconductor layer to form a channel between a source and a drain. The TFT further includes a source-channel interfacial member adjacent to at least the source contact of the device to provide depletion layer control of the operation of the TFT.
1. A vertical thin film transistor comprising:
a substantially planar substrate;
an insulating layer formed on the substrate;
a source formed on the insulating layer
a second insulating layer formed on the source, the second insulating layer forming a vertical well having an inner surface;
a source-channel interfacial member formed on the inner surface of the vertical well and the source;
an n-type semiconductor material formed on the source-channel interfacial member, such that the source is electrically connected to the n-type semiconductor material by the source-channel interfacial member;
a gate dielectric layer formed over the n-type semiconductor material;
a gate formed over the dielectric layer; and
a drain formed on the insulating layer and in electrical contact with the n-type semiconductor material, wherein when the transistor is in an on state current can flow from the source to the drain through the source-channel interfacial member and through a channel formed in the n-type semiconductor material.
2. The vertical thin film transistor according to claim 1 wherein the n-type semiconductor material is selected from the group comprising zinc oxide, tin oxide, indium oxide, indium gallium zinc oxide, gallium oxide and germanium oxide and combinations thereof.
3. The vertical thin film transistor according to claim 1 wherein the transistor is formed as a hexagonal prism.
4. The vertical thin film transistor according to claim 1 wherein the transistor is formed as a rectangular parallelepiped.
5. The vertical thin film transistor according to claim 1 wherein the transistor is formed on a substrate which covers at least a second vertical thin film transistor.
6. The vertical thin film transistor according to claim 1 wherein the source-channel interfacial member is a p-type semiconductor.
7. The vertical thin film transistor according to claim 1 wherein the p-type semiconductor is an oxide formed by catalytic growth of the source.
8. The vertical thin film transistor according to claim 1 wherein the source-channel interfacial member is a piezoelectric induced dipole.
9. The vertical thin film transistor according to claim 1 wherein the source-channel interfacial member is a controllable tunnelling barrier.
10. A vertical thin film transistor comprising:
a substantially planar substrate;
an insulating layer formed on the substrate;
a source formed on the insulating layer;
a source-channel interfacial member formed on the source;
a second insulating layer formed on the source-channel interfacial member and forming a vertical well having an inner surface extending upward from the source-channel interfacial member;
an n-type semiconductor material formed on inner surface of the well and the source-channel interfacial member, wherein the source-channel interfacial member electrically connects the source to the n-type semiconductor material;
a gate dielectric layer formed over the n-type semiconductor material;
a gate formed over the dielectric layer; and
a drain formed on the second insulating layer in electrical contact with the n-type semiconductor material wherein, when the transistor is in an on state current can flow from the source to the drain through the source-channel interfacial member and through a channel formed in the n-type semiconductor material.
11. The vertical thin film transistor according to claim 10 wherein the n-type semiconductor material is selected from the group comprising zinc oxide, tin oxide, indium oxide, indium gallium zinc oxide, gallium oxide and germanium oxide and combinations thereof.
12. The vertical thin film transistor according to claim 10 wherein the transistor is formed as a hexagonal prism.
13. The vertical thin film transistor according to claim 10 wherein the transistor is formed as a rectangular parallelepiped.
14. The vertical thin film transistor according to claim 10 wherein the transistor is formed on a substrate which covers at least a second vertical thin film transistor.
15. The vertical thin film transistor according to claim 10 wherein the source-channel interfacial member is a p-type semiconductor.
16. The vertical thin film transistor according to claim 10 wherein the p-type semiconductor is an oxide formed by catalytic growth of the source.
17. The vertical thin film transistor according to claim 10 wherein the source-channel interfacial member is a piezoelectric induced dipole.
18. The vertical thin film transistor according to claim 10 wherein the source-channel interfacial member is a controllable tunnelling barrier.
19. A thin film transistor comprising:
a substrate;
an insulating layer formed on the substrate;
a source;
a drain formed on the insulating layer and vertically spaced from the source;
an n-type semiconductor material formed on the insulating layer and extending between the source and the drain;
a source-channel interfacial member electrically connecting at least the source to the n-type semiconductor material;
a gate dielectric layer formed over the n-type semiconductor material;
a gate formed over the dielectric layer; and
a second insulating layer, wherein one of the source and the drain are formed on the insulating layer, the second insulating layer is formed on the one of said source and drain, the second insulating layer forming a vertical hollow having an inner surface extending upward from the one of the source and the drain, the source-channel interfacial member forming a layer on the inner surface of the hollow and the portion of the drain within the hollow, the n-type semiconductor material forming a layer on the layer of the source-channel interfacial member, the gate dielectric layer forming a layer on the n-type semiconductor, the gate being formed on the gate dielectric layer and the other of the source and drain being formed on top of the second insulating layer in electrical contact with the source-channel interfacial member and wherein, when the transistor is in an on state current can flow from the source to the drain through the source-channel interfacial member and through a channel formed in the n-type semiconductor material.
20. A thin film transistor comprising:
a substrate;
an insulating layer formed on the substrate;
a source;
a drain formed on the insulating layer and vertically spaced from the source;
an n-type semiconductor material formed on the insulating layer and extending between the source and the drain;
a source-channel interfacial member electrically connecting at least the source to the n-type semiconductor material;
a gate dielectric layer formed over the n-type semiconductor material;
a gate formed over the dielectric layer; and
a second insulating layer and wherein the source is formed on the insulating layer, the source-channel interfacial member is formed on the source, the second insulating layer is formed on the source, the second insulating layer forming a vertical hollow having an inner surface extending upward from the source, the n-type semiconductor material forming a layer on the layer of the source-channel interfacial member and the inner surface of the hollow, the gate dielectric layer forming a layer on the n-type semiconductor material, the gate being formed on the gate dielectric layer and the drain being formed on top of the second insulating layer and in electrical contact with the n-type semiconductor material and wherein, when the transistor is in an on state current can flow from the source to the drain through the source-channel interfacial member and through a channel formed in the n-type semiconductor material.
21. A thin film transistor comprising:
a substrate;
an insulating layer formed on the substrate;
a source;
a drain formed on the insulating layer and vertically spaced from the source;
an n-type semiconductor material formed on the insulating layer and extending between the source and the drain;
a source-channel interfacial member electrically connecting at least the source to the n-type semiconductor material;
a gate dielectric layer formed over the n-type semiconductor material;
a gate formed over the dielectric layer; and
a second insulating layer and wherein the drain is formed on the insulating layer, the second insulating layer is formed on the drain, the second insulating layer forming a vertical hollow having an inner surface extending upward from the drain, the second insulating layer forming a vertical hollow extending upward from the drain and having an inner surface, the n-type semiconductor material forming a layer on the inner surface of the vertical hollow and the drain, the gate dielectric layer forming a layer on the n-type semiconductor and the gate being formed on the gate dielectric layer, the source and the source-channel interfacial material being formed on top of the second insulating layer such that the source-channel interfacial member electrically connects the source to the n-type semiconductor material and wherein, when the transistor is in an on state current can flow from the source to the drain through the source-channel interfacial member and through a channel formed in the n-type semiconductor material.
22. A vertical thin film transistor comprising:
a substantially planar substrate;
an insulating layer formed on the substrate;
a drain formed on the insulating layer;
a second insulating layer formed on the drain and forming a vertical well having an inner surface extending upward from the drain;
an n-type semiconductor material formed on inner surface of the well and the drain;
a gate dielectric layer formed over the n-type semiconductor material;
a gate formed over the dielectric layer; and
a source and a source-channel interfacial member formed on the second insulating layer, the source-channel interfacial member electrically connecting the source to the n-type semiconductor material wherein, when the transistor is in an on state current can flow from the source to the drain through the source-channel interfacial member and through a channel formed in the n-type semiconductor material.
23. The vertical thin film transistor according to claim 22 wherein the n-type semiconductor material is selected from the group comprising zinc oxide, tin oxide, indium oxide, indium gallium zinc oxide, gallium oxide and germanium oxide and combinations thereof.
24. The vertical thin film transistor according to claim 22 wherein the transistor is formed as a hexagonal prism.
25. The vertical thin film transistor according to claim 22 wherein the transistor is formed as a rectangular parallelepiped.
26. The vertical thin film transistor according to claim 22 wherein the transistor is formed on a substrate which covers at least a second vertical thin film transistor.
27. The vertical thin film transistor according to claim 22 wherein the source-channel interfacial member is a p-type semiconductor.
28. The vertical thin film transistor according to claim 22 wherein the p-type semiconductor is an oxide formed by catalytic growth of the source.
29. The vertical thin film transistor according to claim 22 wherein the source-channel interfacial member is a piezoelectric induced dipole.
30. The vertical thin film transistor according to claim 22 wherein the source-channel interfacial member is a controllable tunnelling barrier.