Trench capacitor structure with hybrid filling layer
A capacitor structure that includes a silicon substrate having a trench structure formed therein; a dielectric disposed over a surface of the trench structure, conformal to the surface of the trench structure; and a filling layer disposed over the dielectric layer and into the trench structure, the filling layer including a conductive layer and a polymer layer.
1. A capacitor structure, comprising:
a silicon substrate having a trench structure formed therein;
a dielectric layer disposed over a surface of the trench structure, conformal to said surface of the trench structure; and
a filling layer disposed over the dielectric layer and into the trench structure, the filling layer comprising:
a conductive layer;
a polymer layer; and
a further conductive layer disposed over the polymer layer and into the trench structure,
wherein the conductive layer is disposed between the dielectric layer and the polymer layer, and
wherein a trench depth of the trench structure ranges between 10 and 100 microns, an aspect ratio of the trench structure ranges between 1:10 and 1:60, a thickness of the dielectric layer ranges between 0.6 and 1.5 microns, a thickness of the conductive layer ranges between 10 and 500 nanometers, a thickness of the polymer layer ranges between 150 and 2000 nanometers, and a thickness of the further conductive layer ranges between 10 and 50 nanometers.
2. The capacitor structure of claim 1 , wherein the conductive layer and the polymer layer completely fill the trench structure.
3. The capacitor structure of claim 1 , wherein the further conductive layer comprises a metallic layer.
4. A capacitor structure, comprising:
a silicon substrate having a trench structure formed therein;
a dielectric layer disposed over a surface of the trench structure, conformal to said surface of the trench structure; and
a filling layer disposed over the dielectric layer and into the trench structure, the filling layer comprising:
a conductive layer; and
a polymer layer,
wherein the polymer layer is disposed between the dielectric layer and the conductive layer, and
wherein a trench depth of the trench structure ranges between 10 and 100 microns, an aspect ratio of the trench structure ranges between 1:10 and 1:60, a thickness of the dielectric layer ranges between 0.6 and 1.5 microns, a thickness of the polymer layer ranges between 150 and 3000 nanometers, and a thickness of the conductive layer ranges between 10 and 50 nanometers.
5. The capacitor structure of claim 4 , wherein the dielectric layer comprises a mineral-type dielectric layer.
6. The capacitor structure of claim 5 , wherein the mineral-type dielectric comprises silicon dioxide, silicon nitride, or silicon oxynitride.
7. The capacitor structure of claim 4 , wherein the conductive layer comprises a metallic layer or a polysilicon layer.
8. The capacitor structure of claim 7 , wherein the metallic layer comprises titanium nitride, vanadium nitride, or tungsten nitride.
9. The capacitor structure of claim 4 , wherein the polymer layer comprises Parylene AF-4.
10. A capacitor structure, comprising:
a silicon substrate having a trench structure formed therein;
a dielectric layer disposed over a surface of the trench structure, conformal to said surface of the trench structure; and
a filling layer disposed over the dielectric layer and into the trench structure, the filling layer comprising:
a conductive layer;
a polymer layer; and
a further conductive layer disposed over the polymer layer and into the trench structure,
wherein the conductive layer is disposed between the dielectric layer and the polymer layer,
wherein the further conductive layer is electrically connected to the conductive layer, and
wherein the thickness of the polymer layer is equal to the thickness of the dielectric layer multiplied by the ratio of the breakdown field of the material of the dielectric layer to the breakdown field of the material of the polymer layer.