Capacitance reduction for back-side power rail device
A semiconductor transistor device includes a channel structure, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, a gate contact, and a back-side source/drain contact. The gate structure wraps around the channel structure. The first source/drain epitaxial structure and the second source/drain epitaxial structure are disposed on opposite endings of the channel structure. The gate contact is disposed on the gate structure. The back-side source/drain contact is disposed under the first source/drain epitaxial structure. The first source/drain epitaxial structure has a concave bottom surface contacting the back-side source/drain contact.
1. A semiconductor transistor device, comprising:
a channel structure;
a gate structure overlying the channel structure, wherein a line intersects the gate structure when viewed from a cross-section;
a first source/drain structure and a second source/drain structure disposed on opposite endings of the channel structure, wherein the first source/drain structure and the second source/drain structure are intersected by the line when viewed from the cross-section; and
a back-side source/drain contact disposed under the first source/drain structure.
2. The semiconductor transistor device of claim 1 , wherein the first source/drain structure has a concave bottom surface contacting the back-side source/drain contact.
3. The semiconductor transistor device of claim 1 , further comprising a gate contact disposed on the gate structure.
4. The semiconductor transistor device of claim 1 , further comprising a back-side dielectric cap disposed under and in direct contact with the second source/drain structure.
5. The semiconductor transistor device of claim 4 , wherein the second source/drain structure has a concave bottom surface contacting the back-side dielectric cap.
6. The semiconductor transistor device of claim 4 , wherein the back-side dielectric cap extends under the gate structure.
7. The semiconductor transistor device of claim 4 , wherein the back-side dielectric cap directly contacts the gate structure.
8. The semiconductor transistor device of claim 4 , further comprising a middle isolation structure surrounding the gate structure, the first source/drain structure, and the second source/drain structure.
9. The semiconductor transistor device of claim 8 , further comprising a lower isolation structure disposed under the middle isolation structure and surrounding the back-side dielectric cap.
10. The semiconductor transistor device of claim 1 , further comprising a dielectric sidewall spacer disposed along a sidewall of the back-side source/drain contact.
11. The semiconductor transistor device of claim 1 , further comprising an inner spacer separating the gate structure from the first source/drain structure and the second source/drain structure.
12. The semiconductor transistor device of claim 1 , wherein the channel structure comprises a stack of semiconductor nanowires.
13. A semiconductor transistor device, comprising:
a channel structure;
a gate structure underlying the channel structure;
a first source/drain structure and a second source/drain structure disposed on opposite endings of the channel structure;
a back-side source/drain contact disposed under and contacting the first source/drain structure; and
a back-side dielectric cap disposed under the gate structure.
14. The semiconductor transistor device of claim 13 , wherein the second source/drain structure has a bottom surface located higher than a bottom surface of the gate structure.
15. The semiconductor transistor device of claim 13 , wherein the back-side source/drain contact has a top surface located higher than a bottom surface of the gate structure.
16. The semiconductor transistor device of claim 13 , further comprising a dielectric sidewall spacer disposed between the back-side source/drain contact and the back-side dielectric cap.
17. The semiconductor transistor device of claim 13 , wherein the gate structure comprises:
a gate electrode; and
a gate dielectric between the gate electrode and the channel structure.
18. The semiconductor transistor device of claim 13 , wherein the back-side dielectric cap comprises SiO 2 , SiN, SiCN, SiOCN, Al 2 O 3 , AION, ZrO 2 , HfO 2 , or combinations thereof.
19. A method of forming a semiconductor transistor device, the method comprising:
forming a fin structure over a substrate by alternately stacking first semiconductor layers and second semiconductor layers;
forming a gate structure to cover a first portion of the fin structure and to leave a second portion of the fin structure uncovered;
removing the second portion of the fin structure;
forming a first source/drain epitaxial structure and a second source/drain epitaxial structure on opposite endings of the fin structure which corresponded to the second portion of the fin structure;
removing the substrate to expose the first source/drain epitaxial structure or the second source/drain epitaxial structure; and
forming a back-side source/drain contact under and contacting the first source/drain epitaxial structure or the second source/drain epitaxial structure.
20. The method of claim 19 , wherein forming the back-side source/drain contact comprises:
forming a back-side contact trench; and
filling the back-side contact trench with a sacrificial semiconductor material.