Capacitance reduction for back-side power rail device
A semiconductor transistor device including a channel structure, gate structure, a first source/drain structure, a second source/drain structure, and a back-side source/drain contact. The gate structure overlies the channel structure. The first source/drain structure and the second source/drain structure are disposed on opposite endings of the channel structure. The back-side source/drain contact is disposed under the first source/drain structure. A line lies across the gate structure and the first source/drain structure. The line is parallel to an upper surface of the gate structure.
1 . A semiconductor transistor device, comprising:
a channel structure;
a gate structure overlying the channel structure;
a first source/drain structure and a second source/drain structure disposed on opposite endings of the channel structure; and
a back-side source/drain contact disposed under the first source/drain structure, wherein the back-side source/drain contact has a first width below the first source/drain structure, and a second width below the first width, wherein the second width is less than the first width,
wherein a line lies across the gate structure and the first source/drain structure, the line being parallel to an upper surface of the gate structure.
2 . The semiconductor transistor device of claim 1 , wherein the back-side source/drain contact is directly contacting the first source/drain structure.
3 . The semiconductor transistor device of claim 2 , wherein the back-side source/drain contact is disposed under the gate structure.
4 . The semiconductor transistor device of claim 3 , wherein the gate structure has a lowermost surface that is below a topmost surface of the back-side source/drain contact when viewed from a cross-section.
5 . The semiconductor transistor device of claim 1 , wherein the line lies across the second source/drain structure.
6 . The semiconductor transistor device of claim 1 , wherein the back-side source/drain contact balloons outwards along a surface closest to the first source/drain structure, and wherein the back-side source/drain contact balloons outwards along a surface furthest from the first source/drain structure.
7 . The semiconductor transistor device of claim 6 , wherein the back-side source/drain contact has a width that is minimum at a middle region of the back-side source/drain contact, wherein the middle region is below a topmost surface of the back-side source/drain contact, and wherein the middle region is above a bottommost surface of the back-side source/drain contact.
8 . The semiconductor transistor device of claim 1 , wherein the back-side source/drain contact has a sidewall that faces an outermost sidewall of the second source/drain structure.
9 . The semiconductor transistor device of claim 1 , wherein the back-side source/drain contact has an upper surface that is concave.
10 . A semiconductor transistor device, comprising:
a channel structure having a first side and a second side, the first side opposite to the second side;
a gate structure disposed around the channel structure;
a first source/drain structure disposed on the first side of the channel structure, wherein the first source/drain structure has a concave bottom surface;
a second source/drain structure disposed on the second side of the channel structure, wherein the second source/drain structure has a concave bottom surface; and
a back-side source/drain contact disposed under and contacting the first source/drain structure.
11 . The semiconductor transistor device of claim 10 , further comprising:
a back-side dielectric cap disposed under the gate structure.
12 . The semiconductor transistor device of claim 11 , wherein the back-side dielectric cap laterally surrounds the back-side source/drain contact.
13 . The semiconductor transistor device of claim 12 , wherein the back-side dielectric cap is disposed under the second source/drain structure.
14 . The semiconductor transistor device of claim 13 , wherein the back-side source/drain contact has a concave upper surface.
15 . A method of forming a semiconductor transistor device, the method comprising:
forming a fin structure over a substrate by alternately stacking first semiconductor layers and second semiconductor layers;
forming a first source/drain epitaxial structure and a second source/drain epitaxial structure on opposite sides of the fin structure;
forming a sacrificial source/drain contact under and contacting the first source/drain epitaxial structure;
with the sacrificial source/drain contact in place, removing the substrate and exposing the second source/drain epitaxial structure; and
replacing the sacrificial source/drain contact with a back-side source/drain contact.
16 . The method of claim 15 , further comprising:
flipping the semiconductor transistor device before removing the substrate.
17 . The method of claim 16 , further comprising:
recessing the first source/drain epitaxial structure from a back-side.
18 . The method of claim 17 , wherein after the first source/drain epitaxial structure is recessed, the first source/drain epitaxial structure has a concave surface.
19 . The method of claim 17 , wherein the recession of the first source/drain epitaxial structure occurs before forming the back-side source/drain contact.
20 . The method of claim 15 , wherein the sacrificial source/drain contact is formed by depositing a dielectric material such as silicon nitride.