Method for forming long channel back-side power rail device
A method of forming a semiconductor transistor device. The method comprises forming a channel structure over a substrate and forming a first source/drain structure and a second source/drain structure on opposite sides of the fin structure. The method further comprises forming a gate structure surrounding the fin structure. The method further comprises flipping and partially removing the substrate to form a back-side capping trench while leaving a lower portion of the substrate along upper sidewalls of the first source/drain structure and the second source/drain structure as a protective spacer. The method further comprises forming a back-side dielectric cap in the back-side capping trench.
1. A semiconductor device, comprising:
a first source/drain structure and a second source/drain structure disposed on opposite endings of a channel structure;
a gate structure wrapping around the channel structure; and
a back-side source/drain contact disposed under the first source/drain structure, wherein the back-side source/drain contact is electrically connected to the first source/drain structure along a contact surface, wherein the contact surface extends from a first outer sidewall of the first source/drain structure to a second outer sidewall of the first source/drain structure, and wherein the back-side source/drain contact extends vertically across a plane defined by a bottom surface of the gate structure.
2. The semiconductor device of claim 1 , further comprising:
a front-side interconnect structure disposed above the gate structure, wherein the front-side interconnect structure is on an opposite side from the back-side source/drain contact.
3. The semiconductor device of claim 2 , wherein the front-side interconnect structure is electrically coupled to the gate structure.
4. The semiconductor device of claim 1 , wherein a portion of the back-side source/drain contact that lies above the plane is concave down to the first source/drain structure.
5. The semiconductor device of claim 1 , wherein a bottommost region of the back-side source/drain contact is flared outwards with a greater width than an upper region.
6. The semiconductor device of claim 1 , further comprising:
a power rail disposed below the back-side source/drain contact, wherein the power rail is electrically coupled to the back-side source/drain contact, and wherein the power rail is configured to connect external circuits to the back-side source/drain contact.
7. The semiconductor device of claim 6 , wherein the power rail is below the channel structure, the gate structure, and the first source/drain structure.
8. The semiconductor device of claim 1 , wherein an interconnect structure is disposed above the second source/drain structure, and wherein the interconnect structure is electrically coupled to the second source/drain structure.
9. The semiconductor device of claim 1 , wherein a portion of the gate structure is below the channel structure.
10. A semiconductor device, comprising:
a gate structure disposed around a channel structure;
a first source/drain structure disposed on a first end of the channel structure;
a second source/drain structure disposed on a second end of the channel structure opposite to the first end of the channel structure; and
a back-side source/drain contact disposed under the first source/drain structure and contacting the first source/drain structure along a first interface that concaves down to the first source/drain structure, wherein a width of the back-side source/drain contact increases for a first distance away from the first source/drain structure.
11. The semiconductor device of claim 10 , wherein the width of the back-side source/drain contact decreases after the first distance for a second distance, and wherein the back-side source/drain contact has sidewalls that are substantially straight after the second distance.
12. The semiconductor device of claim 10 , wherein the back-side source/drain contact has an uppermost region that is above a bottommost surface of the second source/drain structure.
13. The semiconductor device of claim 10 , wherein the first source/drain structure has a bottommost region that is above a bottommost region of the second source/drain structure.
14. The semiconductor device of claim 10 , further comprising a power rail disposed along a back surface of the back-side source/drain contact, wherein the power rail is electrically coupled to the back-side source/drain contact, and wherein the power rail has a width larger than the width of the back-side source/drain contact.
15. The semiconductor device of claim 10 , wherein the back-side source/drain contact has a ledge that extends outwards, and wherein the ledge has a width smaller than 5 nm.
16. The semiconductor device of claim 15 , wherein the ledge has a height smaller than 20 nm.
17. The semiconductor device of claim 10 , wherein a bottommost surface of the second source/drain structure is coplanar to a bottommost surface of the gate structure.
18. A semiconductor device comprising:
a channel structure disposed within a substrate;
a first source/drain structure disposed on an end of the channel structure;
a back-side source/drain contact disposed under and electrically coupled to the first source/drain structure, wherein the back-side source/drain contact has a first ledge extending outwards from a first side and a second ledge extending outwards from a second side opposite to the first side; and
a dielectric liner disposed along a bottom surface and a top surface of the first ledge, the dielectric liner being positioned below the channel structure.
19. The semiconductor device of claim 18 , wherein the dielectric liner is positioned below the channel structure at a first region, the first region being laterally adjacent to a furthest extending point of the first ledge.
20. The semiconductor device of claim 18 , wherein the top surface of the first ledge is continuous with the top surface of the back-side source/drain contact.