IP Library › Granted Patent US 11,973,044

Granted Patent B2

US 11,973,044 · App. 17/560,610 · Granted Apr 30, 2024

Non-volatile memory with efficient signal routing

Inventors: Shiqian Shao (Fremont, CA); Fumiaki Toyama (Cupertino, CA); Tuan Pham (San Jose, CA)

H01L24/08 H01L24/80 H01L25/0657 H01L25/18 H01L25/50 H01L2224/08145 H01L2224/80895 H01L2224/80896 H01L2924/1431 H01L2924/14511

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Quick Facts

Patent No.: US 11,973,044
App. No.: 17/560,610
Granted: Apr 30, 2024
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

An integrated memory assembly comprises a control die bonded to a memory die. The memory die includes multiple non-volatile memory structures (e.g., planes, arrays, groups of blocks, etc.), each comprising a stack of alternating conductive and dielectric layers forming staircases at one or more edges of the non-volatile memory structures. The non-volatile memory structures are positioned with gaps between the non-volatile memory structures such that the gaps separate the staircases of adjacent non-volatile memory structures. Metal interlayer segments positioned in the gaps are connected to a top metal layer positioned above non-volatile memory structures and to one or more electrical circuits on the control die via zero, one or more other metal layers/segments.

Claims (140)

1. An integrated memory assembly apparatus, comprising:

a first semiconductor die comprising:

a first non-volatile memory structure adjacent a second non-volatile memory structure with a gap between the first non-volatile memory structure and the second non-volatile memory structure, the first non-volatile memory structure having a stack of alternating conductive and dielectric layers forming a first staircase at an edge of the first non-volatile memory structure facing the second non-volatile memory structure, the second non-volatile memory structure having a stack of alternating conductive and dielectric layers forming a second staircase at an edge of the second non-volatile memory structure facing the first non-volatile memory structure,

a first top metal layer positioned above the first non-volatile memory structure and the second non-volatile memory structure,

a first bottom metal layer positioned below the first non-volatile memory structure and the second non-volatile memory structure, and

a first metal interlayer segment positioned in the gap, positioned between the first staircase and the second staircase, connected to the first top metal layer and connected to the first bottom metal layer; and

a second semiconductor die physically connected to the first semiconductor die, the second semiconductor die comprising:

an electrical circuit, and

a metal transmission layer connected to the electrical circuit and the first metal interlayer segment via the first bottom metal layer, the metal transmission layer is configured to communicate a signal from the first top metal layer to the electrical circuit.

2. The apparatus of claim 1 , wherein:

the first semiconductor die further comprises an I/O pad on a top surface of the first semiconductor die at a first side of the first semiconductor die; and

the first top metal layer is connected to the I/O pad and extends across the first semiconductor die from the I/O.

3. The apparatus of claim 1 , wherein:

the first top metal layer is directly on top of at least a portion of the gap and extends parallel to the gap.

4. The apparatus of claim 1 , wherein:

the first top metal layer is directly on top of at least a portion of the gap and extends perpendicular to the gap.

5. The apparatus of claim 1 , wherein:

the first semiconductor die further comprises a first interface connected to the bottom metal layer; and

the second semiconductor die further comprises:

a second interface in electrical communication with the first interface,

a second top metal layer below the second interface and above the metal transmission layer, and

a second bottom metal layer below the metal transmission layer;

the metal transmission layer is connected to the first metal interlayer segment via the first bottom metal layer, the first interface, the second interface and the second top metal layer;

a first electrical pathway exists from the first top metal layer through the first metal interlayer segment to the first bottom metal layer, to the second top metal layer via the first interface and the second interface, to the metal transmission layer, along the metal transmission layer to the electrical circuit on the second semiconductor die via the second bottom layer.

6. The apparatus of claim 5 , wherein:

the first semiconductor die has a first end and a second end opposite the first end;

the first semiconductor die has a middle that is between the first end of the first semiconductor die and the second end of the first semiconductor die;

the second semiconductor die has a first end corresponding in location to the first end of the first semiconductor die;

the second semiconductor die has a second end corresponding in location to the second end of the first semiconductor die;

the second semiconductor die has a middle that is between the first end of the second semiconductor die and the second end of the second semiconductor die;

the first top metal layer runs from the first end of the first semiconductor die to at least the middle of the first semiconductor die;

the first top metal layer connects to I/O pads at the first end of the first semiconductor die;

the first metal interlayer segment is positioned at and connects to the first top metal layer at the middle of the first semiconductor die; and

the first electrical pathway runs from the second interface to the metal transmission layer and then to the electrical circuit at the middle of the second semiconductor die.

7. The apparatus of claim 5 , wherein:

the first semiconductor die has a first end and a second end opposite the first end;

the first semiconductor die has a middle that is between the first end of the first semiconductor die and the second end of the first semiconductor die;

the second semiconductor die has a first end corresponding in location to the first end of the first semiconductor die;

the second semiconductor die has a second end corresponding in location to the second end of the first semiconductor die;

the second semiconductor die has a middle that is between the first end of the second semiconductor die and the second end of the second semiconductor die;

the first top metal layer runs from the first end of the first semiconductor die to the second end of the first semiconductor die;

the first top metal layer connects to I/O pads at the first end of the first semiconductor die;

the first metal interlayer segment is positioned at and connects to the first top metal layer at the second end of the first semiconductor die; and

the first electrical pathway runs from the second interface to the metal transmission layer and then to the electrical circuit at the second end of the second semiconductor die.

8. The apparatus of claim 1 , wherein:

the first semiconductor die comprises additional non-volatile memory structures each having additional staircases with additional gaps between the additional staircases and additional metal interlayer segments positioned in the additional gaps and connecting to the first top metal layer.

9. The apparatus of claim 1 , wherein:

the first semiconductor die is a memory die; and

the second semiconductor die is a control die bonded to the memory die to form an integrated memory assembly with the memory die.

10. The apparatus of claim 1 , wherein:

the first non-volatile memory structure and the second non-volatile memory structure are three dimensional NAND arrays with vertical charge trapping layers.

11. The apparatus of claim 1 , wherein:

the second semiconductor die includes a substrate and sense amplifiers positioned on the substrate, the electrical circuit is positioned between sense amplifiers; and

the second semiconductor die further comprises a second top metal layer above the metal transmission layer and a second bottom metal layer below the metal transmission layer.

12. The apparatus of claim 1 , wherein:

the first top metal layer is configured to carry one of a global power signal, global data signal, and a global command signal; and

the first non-volatile memory structure and the second non-volatile memory structure are planes of non-volatile memory cells, each plane includes multiple blocks of the memory cells.

13. A method, comprising:

fabricating a memory die, comprising:

creating a first plane with a first staircase at an edge of the first plane,

creating a second plane with a second staircase at an edge of the second plane, the edge of the first plane is positioned adjacent to the edge of the second plane with a gap between the edge of the first plane and the edge of the second plane such that the first staircase is adjacent the second staircase with the gap being between the first staircase and the second staircase,

adding a first top metal layer positioned above the first plane and the second plane,

adding a first bottom metal layer positioned below the first plane and the second plane,

adding a first metal interlayer segment positioned in the gap, and connecting the first top metal layer to the first bottom metal layer via the first metal interlayer segment, and

adding a first interface connected to the bottom metal layer;

fabricating a control die, comprising:

adding a second interface in electrical communication with the first interface,

adding a second top metal layer below the second interface,

adding a second middle metal layer below the second top metal layer,

adding a second bottom metal layer below the second middle metal layer, and

adding a plurality of electrical circuits to a substrate below the second bottom metal layer; and

bonding the control die to the memory die to form a first electrical pathway from the first top metal layer through the first metal interlayer segment to the first bottom layer, to the second top metal layer via the first interface and the second interface, to the second middle metal layer, along the second middle metal layer to one or more of the electrical circuits on the control die via the second bottom layer.

14. The method of claim 13 , wherein:

the memory die has a first end and a second end opposite the first end;

the memory die has a middle that is between the first end of the memory die and the second end of the memory die;

the control die has a first end corresponding in location to the first end of the memory die;

the control die has a second end corresponding in location to the second end of the memory die;

the control die has a middle that is between the first end of the control die and the second end of the control die;

the first top metal layer runs from the first end of the memory die to the second end of the memory die;

the first top metal layer connects to I/O pads at the first end of the memory die;

the first metal interlayer segment is positioned at and connects to the first top metal layer at the middle of the memory die; and

the first electrical pathway runs from the second interface to the second middle metal layer and then to at least one electrical circuit of the plurality of electrical circuits at the middle of the control die.

15. The method of claim 13 , wherein:

the memory die has a first end and a second end opposite the first end;

the memory die has a middle that is between the first end of the memory die and the second end of the memory die;

the control die has a first end corresponding in location to the first end of the memory die;

the control die has a second end corresponding in location to the second end of the memory die;

the control die has a middle that is between the first end of the control die and the second end of the control die;

the first top metal layer runs from the first end of the memory die to the second end of the memory die;

the first top metal layer connects to I/O pads at the first end of the memory die;

the first metal interlayer segment is positioned at and connects to the first top metal layer at the second end of the memory die; and

16. An integrated memory assembly apparatus, comprising:

a memory die comprising:

a first non-volatile memory structure with a first staircase at an edge of the first non-volatile memory structure,

a second non-volatile memory structure with a second staircase at an edge of the second non-volatile memory structure, the edge of the first non-volatile memory structure is positioned adjacent to the edge of the second non-volatile memory structure with a gap between the edge of the first non-volatile memory structure and the edge of the second non-volatile memory structure such that the first staircase is adjacent the second staircase with the gap being between the first staircase and the second staircase,

a first top metal layer positioned above the first non-volatile memory structure and the second non-volatile memory structure,

a first bottom metal layer positioned below the first non-volatile memory structure and the second non-volatile memory structure,

a first metal interlayer segment positioned in the gap and connecting the first top metal layer to the first bottom metal layer, and

a first interface connected to the bottom metal layer; and

a control die bonded to the memory die, the control die comprising:

a second interface in electrical communication with the first interface,

a second top metal layer below the second interface,

a second middle metal layer below the second top metal layer,

a second bottom metal layer below the second middle metal layer, and

a plurality of electrical circuits below the second bottom metal layer;

a first electrical pathway exists from the first top metal layer through the first metal interlayer segment to the first bottom metal layer, to the second top metal layer via the first interface and the second interface, to the second top metal layer, to the second middle metal layer, along the second middle metal layer to one or more of the electrical circuits on the control die via the second bottom layer.

17. The apparatus of claim 16 , wherein: