3D stacked die test architecture
This disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The test architecture uses an improved TAP design to facilitate the testing of parallel test circuits within the die.
1. A device comprising:
a parallel test data input (PTDI) bus;
a parallel test data input/output (PTDIO) bus;
a first surface coupled to the PTDI bus and the PTDIO bus;
a second surface opposite the first surface, wherein the second surface is coupled to the PTDI bus and the PTDIO bus;
a first parallel test circuit coupled to the PTDI bus, wherein the first parallel test circuit includes a first parallel test data output (PTDO);
a second parallel test circuit coupled to the PTDI bus, wherein the second parallel test circuit includes a second PTDO;
a first comparator coupled to the first PTDO and the PTDIO bus, wherein the first comparator includes a first comparator output;
a second comparator coupled to the second PTDO and the PTDIO bus, wherein the second comparator includes a second comparator output;
a first gate circuit coupled to the first comparator output, wherein the first gate circuit includes an output coupled to the PTDIO bus; and
a second gate circuit coupled to the second comparator output, wherein the second gate circuit includes an output coupled to the PTDIO bus.
2. The device of claim 1 , further comprising:
a first buffer coupled to the first PTDO and the PTDIO bus; and
a second buffer coupled to the second PTDO and the PTDIO bus.
3. The device of claim 1 , further comprising a tri-state buffer coupled to the output of the first gate circuit, wherein the tri-state buffer includes an output coupled to the PTDIO bus.
4. The device of claim 3 , further comprising an enable line coupled to the first comparator, the second comparator, and the tri-state buffer.
5. The device of claim 1 ,
wherein the PTDI bus includes a number (N) of lines, and
wherein the PTDIO bus includes N+1 lines.
6. The device of claim 1 , wherein the PTDI bus comprises a first line coupled to the first parallel test circuit and coupled to the second parallel test circuit.
7. The device of claim 6 , wherein the PTDIO bus further comprises a second line coupled to the output of the first gate circuit and coupled to the output of the second gate circuit.
8. The device of claim 1 , further comprising an enable line coupled to the first comparator and the second comparator.
9. The device of claim 8 ,
wherein the first comparator is configured to compare first data on the first PTDO and second data from the PTDIO bus in response to a signal on the enable line, and
wherein the second comparator is configured to compare third data on the second PTDO and fourth data from the PTDIO bus in response to the signal on the enable line.
10. The device of claim 9 , wherein the first comparator is configured to:
detect a first mismatch between the first data and the second data; and
output a first fail signal to the first gate circuit in response to detecting the first mismatch, and
wherein the first gate circuit is configured to output a first compare failure output (CFO) in response to the first fail signal.
11. The device of claim 10 ,
wherein the second comparator is configured to:
detect a second mismatch between the third data and the fourth data;
output a second fail signal to the second gate circuit in response to detecting the second mismatch, and
wherein the second gate circuit is configured to output a compare failure output (CFO) in response to the second fail signal.
12. The device of claim 1 , further comprising a test access port (TAP) circuit coupled to the first comparator and the second comparator.
13. The device of claim 12 , wherein the TAP circuit comprises an enable output coupled to the first comparator and the second comparator.
14. The device of claim 12 ,
wherein the TAP circuit comprises a first enable output,
wherein the device further comprises:
a first buffer coupled to the first enable output, the first PTDO, and the PTDIO bus; and
a second buffer coupled to the first enable output, the second PTDO, and the PTDIO bus, and
wherein the TAP circuit further comprises a second enable output coupled to the first comparator and the second comparator.
15. The device of claim 14 ,
wherein the first buffer is configured to:
receive first test data on the first PTDO; and
output the first test data to the PTDIO in response to a signal at the first enable output, and
wherein the second buffer is configured to:
receive second test data on the second PTDO; and
output the second test data to the PTDIO in response to the signal at the first enable output.
16. The device of claim 14 , further comprising a tri-state buffer coupled to the second enable output and the output of the first gate circuit,
wherein the tri-state buffer includes an output coupled to the PTDIO bus.
17. The device of claim 1 ,
wherein the PTDI bus includes a first set of through-silicon vias (TSVs) extending between the first surface and the second surface, and
wherein the PTDIO bus includes a second set of TSVs extending between the first surface and the second surface.
18. A device comprising:
a parallel test data input (PTDI) bus having a first PTDI line and a second PTDI line;
a parallel test data input/output (PTDIO) bus having a first PTDIO line, a second PTDIO line, and a third PTDIO line;
a first surface coupled to the PTDI bus and the PTDIO bus;
a second surface opposite the first surface, wherein the second surface is coupled to the PTDI bus and the PTDIO bus;
a parallel test circuit coupled to the first PTDI line and the second PTDI line, wherein the parallel test circuit includes a first parallel test data output (PTDO) and a second PTDO;
a first comparator coupled to the first PTDO and the first PTDIO line, wherein the first comparator includes a first comparator output;
a second comparator coupled to the second PTDO and the second PTDIO line, wherein the second comparator includes a second comparator output; and
a gate circuit coupled to the first comparator output and the second comparator output,
wherein the gate circuit includes an output coupled to the third PTDIO line.
19. The device of claim 18 , wherein the gate circuit is configured to output a compare failure output (CFO) in response to the first comparator output or the second comparator output.
20. The device of claim 18 , further comprising:
a test access port (TAP) circuit coupled to the first comparator and the second comparator and operable to enable the first comparator and the second comparator.