Field effect transistor with controllable resistance
A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer.
1. A semiconductor device comprising:
a source terminal;
a drain terminal, wherein the source terminal and the drain terminal are formed on either sides of a channel region designated on a substrate;
an energy barrier adjacent to the source terminal and the channel region;
a conductive gate stack formed over the channel region, the conductive gate stack including;
a first gate dielectric layer on the channel region;
a second gate dielectric layer on the first gate dielectric layer;
a charge storage layer between the first gate dielectric layer and the second gate dielectric layer,
wherein the semiconductor device is configured to store a connection weight corresponding to a crosspoint device.
2. The semiconductor device of claim 1 , further comprising a capacitor configured to store a charge indicative of the connection weight.
3. The semiconductor device of claim 2 , wherein the channel region includes a channel having a first amount of dopants and the energy barrier has a second amount of dopants greater than the first amount of dopants of the channel.
4. The semiconductor device of claim 3 , wherein the energy barrier and the channel are doped with n-type dopants and the source terminal and the drain terminal are doped with p-type dopants.
5. The semiconductor device of claim 4 , wherein the energy barrier has a size smaller than each of the source terminal and the channel.
6. The semiconductor device of claim 5 , wherein the gate stack includes a pair of opposing spacers, wherein at least one of the spacers is on an upper surface of the energy barrier.
7. The semiconductor device of claim 1 , wherein the charge storage layer comprises polysilicon.
8. The semiconductor device of claim 7 , wherein the gate stack includes a conductive material layer on the second gate dielectric layer.
9. A semiconductor device comprising:
a source terminal;
a drain terminal, wherein the source terminal and the drain terminal are formed on either sides of a channel region designated on a substrate;
an energy barrier adjacent to the source terminal and the channel region; and
a conductive gate stack formed over the channel region, the conductive gate stack including:
at least one gate dielectric layer on the channel region; and
a gate electrode on the at least one gate dielectric layer;
a capacitor connected directly to the gate electrode and configured to store a charge indicative of a connection weight corresponding to a crosspoint device.
10. The semiconductor device of claim 9 , wherein the capacitor includes a first terminal connected directly to the gate electrode and an opposing second terminal connected directly to a ground potential.