Methods and systems for selectively enabling/disabling memory dies

1. A method for selectively activating or deactivating one or more memory dies of a memory array, comprising:

detecting a first enable signal at a memory die of the memory array;

detecting a first data signal on one or more input/output (I/O) receivers of the memory die;

responsive to detecting at least the first enable signal, latching, at each of a first one or more rising or falling edges of a clock signal, a bit value encoded in the first data signal to obtain a first bit pattern;

obtaining a second bit pattern; and

based on a comparison of the first bit pattern to the second bit pattern, activating the one or more I/O receivers of the memory die.

2. The method of claim 1 , further comprising:

detecting a second enable signal at the memory die,

wherein latching the bit value encoded in the first data signal to obtain the first bit pattern is responsive to detecting the first and second enable signals.

3. The method of claim 2 , wherein the first enable signal is a command latch enable signal asserted at a logic HIGH level and the second enable signal is an address latch enable signal asserted at a logic HIGH level.

4. The method of claim 2 , further comprising comparing the first bit pattern to the second bit pattern responsive to detecting the first and second enable signals.

5. The method of claim 1 , further comprising:

decoding the first bit pattern to obtain an address code indicative of one or more memory dies of the memory array; and

decoding the second bit pattern to obtain a chip address that identifies the memory die.

6. The method of claim 5 , further comprising:

determining that the memory die identified by the chip address is one of the one or more memory dies indicated in the address code by comparing the address code to the chip address,

wherein activating the one or more I/O receivers of the memory die is responsive to the determination.

7. The method of claim 5 , further comprising:

determining that the memory die identified by the chip address is different than the one or more memory dies indicated in the address code by comparing the address code to the chip address; and

deactivating the one or more I/O receivers of the memory die responsive to the determination.

8. The method of claim 1 , wherein enabling the one or more I/O receivers comprises latching a status bit value into a register on the memory die, the method further comprising:

detecting a third enable signal at the memory die;

obtaining the status bit value from the register;

responsive to detecting at least the third enable signal and obtaining the status bit value, detecting a second data signal on the I/O receivers; and

decoding a bit pattern obtained from the second data signal as I/O data.

9. The method of claim 1 , wherein the second bit pattern is hard coded into the memory die.

10. A memory die, comprising:

one or more input/output (I/O) receivers;

a first enable signal receiver; and

a control circuit configured to:

detect a first enable signal, receiver from a storage controller, on the first enable signal;

detect a first data signal on the one or more input/output (I/O) receivers;

responsive to detecting at least the first enable signal, latch, at each of a first one or more rising or falling edges of a clock signal, a bit value encoded in the first data signal to obtain a first bit pattern;

obtain a second bit pattern; and

based on a comparison of the first bit pattern to the second bit pattern, activate the one or more I/O receivers.

11. The memory die of claim 10 , further comprising:

a second enable signal receiver,

wherein the control circuit is further configured to:

detect a second enable signal, from the storage controller, on the second enable signal receiver,

wherein latching the bit value encoded in the first data signal to obtain the first bit pattern is responsive to detecting the first and second enable signals.

12. The memory die of claim 11 , wherein the first enable signal is a command latch enable signal asserted at a logic HIGH level and the second enable signal is an address latch enable signal asserted at a logic HIGH level.

13. The memory die of claim 11 , wherein the control circuit is further configured to compare the first bit pattern to the second bit pattern responsive to detecting the first and second enable signals.

14. The memory die of claim 10 , wherein the control circuit is further configured to:

decode the first bit pattern to obtain an address code indicative of one or more memory dies; and

decode the second bit pattern to obtain a chip address that identifies the memory die.

15. The memory die of claim 14 , wherein the control circuit is further configured to:

determine that the memory die identified by the chip address is one of the one or more memory dies indicated in the address code by comparing the address code to the chip address,

wherein activating the one or more I/O receivers of the memory die is responsive to the determination.

16. The memory die of claim 14 , wherein the control circuit is further configured to:

determine that the memory die identified by the chip address is different than the one or more memory dies indicated in the address code by comparing the address code to the chip address; and

deactivate the one or more I/O receivers of the memory die responsive to the determination.

17. The memory die of claim 10 , wherein enabling the one or more I/O receivers comprises latching a status bit value into a register on the memory die, wherein the control circuit is further configured to:

detect a third enable signal;

obtain the status bit value from the register;

responsive to detecting at least the third enable signal and obtaining the status bit value, detect a second data signal on the I/O receivers; and

decode a bit pattern obtained from the second data signal as I/O data.

18. The memory die of claim 10 , wherein the second bit pattern is hard coded into the memory die.

19. A memory device, comprising:

one or more signal generators configured to generate a first enable signal and a clock signal; and

a memory array comprising a plurality of memory dies, each memory die comprising a control circuit configured to:

detect a first enable signal asserted at a first logic level and a second enable signal asserted at the first logic level;

responsive to detecting the first and second enable signals:

detect a first data signal over input/out (I/O) pins;

decode a first bit pattern encoded into the first data signal to obtain an address code indicative of one or more memory dies of the memory array;

decode a second bit pattern hardcoded into the respective memory die to obtain a chip address of the respective memory die;

determine whether the respective memory die is one of the one or more memory dies indicated in the address code; and

enable or disable the respective memory die based on the determination.

20. The memory device of claim 19 , wherein enabling the respective memory die comprises activating the I/O pins for performing data operations on the memory die, and wherein disabling the respective memory die deactivating the I/O pins.