Location dependent sense time offset parameter for improvement to the threshold voltage distribution margin in non-volatile memory structures

1. A method for performing a program verify memory in a non-volatile memory system, comprising the steps of:

preparing a memory structure that includes:

an array of memory cells that are arranged in a plurality of NAND strings and in a plurality of word lines,

the NAND stings including memory holes and extending between respective bit lines and a common source line,

each of the memory cells including a control gate and a charge storing element,

the plurality of NAND strings including outer strings that are physically arranged on opposite sides of inner NAND strings;

determining a location of the target memory cell within the memory structure;

in response to the target memory cell being located in one of the outer NAND strings, setting an offset parameter time value at a first magnitude, and in response to the target memory cell being located in one of the inner NAND strings, setting the offset parameter time value at a second magnitude that is different than the first magnitude; and

respect to each programmable memory state:

applying a first sense signal at a first point in time; and

applying a second sense signal at a second point in time, wherein a time interval between the first and second points in time is equal to a predetermined optimal time period that is adjusted by the offset parameter time value.

2. The method according to claim 1 , wherein the memory structure is a vertical three-dimensional NAND-type array.

3. The method according to claim 2 , wherein the plurality of NAND strings exhibit variations in their respective cell structures.

4. The method according to claim 2 , wherein:

the first magnitude is equal to zero.

5. The method according to claim 1 , wherein the first magnitude is mathematically proportional to the second magnitude.

6. A memory controller, comprising:

a first port configured to couple to a non-volatile memory structure, the memory structure comprising at least one vertical three-dimensional NAND-type memory array of memory cells;

the memory cells being arranged in a plurality of NAND strings and in a plurality of word lines;

the NAND strings including memory holes that extend between respective bit lines and a common source line;

each of the memory cells including a control gate and a charge storing element;

the plurality of NAND strings including outer strings that are physically arranged on opposite sides of inner NAND strings;

and

during program verify of a target memory cell, the memory controller being configured to:

initiate a program verify operation with respect to the target memory cell;

determine a location of the target memory cell within the memory array;

in response to the target memory cell being located in one of the outer NAND strings, set an offset parameter time value at a first magnitude, and in response to the target memory cell being located in one of the inner NAND strings, set the offset parameter time value at a second magnitude that is different than the first magnitude; and

with respect to each programmable memory state:

apply a first sense signal at a first point in time; and

apply a second sense signal at a second point in time, wherein a time interval between the first and the second points in time is equal to a predetermined optimal time period that is adjusted by the offset parameter time value.

7. The memory controller according to claim 6 , wherein the plurality of NAND strings exhibit variations in their respective cell structures.

8. The memory controller according to claim 6 , wherein:

the first magnitude is set equal to zero.

9. The memory controller according to claim 6 , wherein the first magnitude is mathematically proportional to the second magnitude.

10. A non-volatile memory system, comprising:

a memory structure that comprises at least one vertical three-dimensional NAND-type memory array having a target memory cell, the memory structure including;

an array of memory cells that are arranged in a plurality of NAND strings and in a plurality of word lines,

the NAND stings including memory holes that extend between respective bit lines and a common source line,

each of the memory cells including a control gate and a charge storing element,

the plurality of NAND strings including outer strings that are physically arranged on opposite sides of inner NAND strings;

a memory controller coupled to the memory structure, the memory controller being configured to:

initiate a program verify operation with respect to the target memory cell;

determine a location of the target memory cell within the memory array;

in response to the target memory cell being located in one of the outer NAND strings, set an offset parameter time value at a first magnitude, and in response to the target memory cell being located in one of the inner NAND strings, set the offset parameter time value at a second magnitude that is different than the first magnitude; and

with respect to each programmable memory state:

apply a first sense signal at a first point in time; and

apply a second sense signal at a second point in time, wherein a time interval between the first and the second points in time is equal to a predetermined optimal time period that is adjusted by the offset parameter time value.

11. The non-volatile memory system according to claim 10 , wherein the plurality of memory strings exhibit variations in their respective cell structures.

12. The non-volatile memory system according to claim 10 , wherein:

the second magnitude is equal to zero.