Photodetector
A sensor includes a first substrate including at least a first pixel. The first pixel includes an avalanche photodiode to convert incident light into electric charge and includes an anode and a cathode. The cathode is in a well region of the first substrate. The first pixel includes an isolation region that isolates the well region from at least a second pixel that is adjacent to the first pixel. The first pixel includes a hole accumulation region between the isolation region and the well region. The hole accumulation region is electrically connected to the anode.
1. A light detecting device, comprising:
an on-chip lens;
a first chip, including:
a first semiconductor substrate including a first avalanche photodiode, wherein the first avalanche photodiode includes:
a well region;
a first semiconductor region of a first conductivity type;
a second semiconductor region of a second conductivity type; and
a third semiconductor region of the first conductivity type, wherein the second and third semiconductor regions are at a surface opposite to a light-receiving surface of the first semiconductor substrate; and
a first wiring layer including a first wiring and a second wiring; and
a second chip stacked on the first chip, the second chip including:
a second semiconductor substrate including a circuit; and
a second wiring layer including a third wiring and a fourth wiring,
wherein the third wiring and the fourth wiring do not extend to the second semiconductor substrate,
wherein a part of the well region is disposed between the on-chip lens and the first semiconductor region in a cross-sectional view,
wherein the first semiconductor region is disposed between the part of the well region and the second semiconductor region in the cross-sectional view,
wherein a surface of the first wiring layer of the first chip is connected to a surface of the second wiring layer of the second chip,
wherein the second semiconductor region is electrically connected to the first wiring,
wherein the third semiconductor region is electrically connected to the second wiring,
wherein the first wiring of the first wiring layer of the first chip is directly bonded to the third wiring of the second wiring layer of the second chip to electrically connect the second semiconductor region to the third wiring of the second wiring layer of the second chip along an interface between the first chip and the second chip, and
wherein the second wiring of the first wiring layer of the first chip is directly bonded to the fourth wiring of the second wiring layer of the second chip to electrically connect the third semiconductor region to the fourth wiring of the second wiring layer of the second chip along the interface between the first chip and the second chip.
2. The light detecting device of claim 1 , wherein the second semiconductor region is surrounded by the third semiconductor region in a plan view.
3. The light detecting device of claim 2 , wherein the third semiconductor region is between a trench and the second semiconductor region.
4. The light detecting device of claim 1 , wherein the first avalanche photodiode of the first chip is electrically connected to the circuit of the second chip.
5. The light detecting device of claim 2 , wherein a second part of the well region is between the second semiconductor region and the third semiconductor region.
6. The light detecting device of claim 1 , wherein the first conductivity type is p-type and the second conductivity type is n-type.
7. A light detecting device, comprising:
an on-chip lens;
a first chip including:
a first semiconductor substrate including a first avalanche photodiode, wherein the first avalanche photodiode includes:
a well region;
a first semiconductor region of a first conductivity type;
a second semiconductor region of a second conductivity type, wherein the second semiconductor region is at a surface opposite to a light-receiving surface of the first semiconductor substrate;
an isolation region surrounding a periphery of the first avalanche photodiode, wherein a hole accumulation region is disposed between the isolation region and the well region; and
a first wiring layer including a first wiring and a second wiring; and
a second chip stacked on the first chip, the second chip including:
a second semiconductor substrate including a circuit; and
a second wiring layer including a third wiring and a fourth wiring,
wherein the third wiring and the fourth wiring do not extend to the second semiconductor substrate
wherein a part of the well region is disposed between the on-chip lens and the first semiconductor region in a cross-sectional view,
wherein the first semiconductor region is disposed between the part of the well region and the second semiconductor region in the cross-sectional view,
wherein a surface of the first wiring layer of the first chip is connected to a surface of the second wiring layer of the second chip,
wherein the second semiconductor region is electrically connected to the first wiring,
wherein a third semiconductor region is electrically connected to the second wiring,
wherein the first wiring of the first wiring layer of the first chip is directly bonded to the third wiring of the second wiring layer of the second chip to electrically connect the second semiconductor region to the third wiring of the second wiring layer of the second chip along an interface between the first chip and the second chip, and
wherein the second wiring of the first wiring layer of the first chip is directly bonded to the fourth wiring of the second wiring layer of the second chip to electrically connect the third semiconductor region to the fourth wiring of the second wiring layer of the second chip along the interface between the first chip and the second chip.
8. The light detecting device of claim 7 , further comprising:
a third semiconductor region of the first conductivity type, wherein the second semiconductor region is surrounded by the third semiconductor region in a plan view.
9. The light detecting device of claim 8 , wherein the third semiconductor region is between a trench and the second semiconductor region.
10. The light detecting device of claim 7 , wherein the first avalanche photodiode of the first chip is electrically connected to the circuit of the second chip.
11. The light detecting device of claim 8 , wherein a second part of the well region is between the second semiconductor region and the third semiconductor region.
12. The light detecting device of claim 7 , wherein the first conductivity type is p-type and the second conductivity type is n-type.