IP Library › Granted Patent US 12,046,619
Granted Patent B2
US 12,046,619 · App. 17/014,891 · Granted Jul 23, 2024

Solid-state imaging device, manufacturing method of solid-state imaging device, and electronic apparatus

Inventor: Kunihiko Izuhara (Kanagawa, JP)
Assignee: Sony Corporation
H01L27/14634H01L27/14618H01L27/1464H01L27/1469H01L2224/48091H01L2224/48227H01L2224/49113
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,046,619
App. No.
17/014,891
Granted
Jul 23, 2024
Kind
B2
Abstract

There is provided a solid-state imaging device including a first substrate having a pixel circuit including a pixel array unit formed thereon, and a second substrate having a plurality of signal processing circuits formed thereon so as to be arranged through a scribe region. The first substrate and the second substrate are stacked.

Claims (53)

1. A light detecting device, comprising:

a first section including:

a first substrate layer at a light incident side of the first section, the first substrate layer including at least a photoelectric conversion region configured to output a pixel signal; and

a first wiring layer at a side opposite the light incident side of the first section; and

a second section including:

first and second regions separated by a separation region;

the first region including:

a second substrate layer including a logic portion configured to process a first signal based on the pixel signal, and a second wiring layer; and

the second region including:

a third substrate layer including a memory portion configured to store pixel data based on the first signal, and a third wiring layer,

wherein the memory portion and the logic portion are provided beneath the first wiring layer, the second wiring layer and the third wiring layer in a cross-sectional view,

wherein the first and second sections are bonded together such that the first and second wiring layers face each other and the first and third wiring layers face each other, and

wherein the first and second substrate layers are electrically connected through the first and second wiring layers via a first wire extending through the first substrate to the second substrate and the first and third substrate layers are electrically connected through the first and third wiring layers via a second wire extending through the first substrate to the third substrate.

2. The light detecting device according to claim 1 , wherein a size of the first region and a size of the second region are each smaller than a size of the first section.

3. A light detecting device, comprising:

a first section including:

a first substrate layer at a light incident side of the first section, the first substrate layer including at least a photoelectric conversion region configured to output a pixel signal; and

a first wiring layer at a side opposite the light incident side of the first section; and

a second section including:

a second substrate layer including first and second regions;

the first region including a first logic portion configured to generate first pixel data based on the pixel signal; and

the second region including a second logic portion configured to generate second pixel data based on the first pixel data; and

a second wiring layer,

wherein the first logic portion and the second logic portion are provided beneath the first and second wiring layers in a cross-sectional view,

wherein the first and second sections are bonded together such that the first and second wiring layers face each other, and

wherein the first and second substrate layers are electrically connected through the first and second wiring layers via a first wire extending through the first substrate to the second substrate.

4. The light detecting device according to claim 3 , wherein the first region is electrically connected to the second region.

5. The light detecting device according to claim 3 , wherein a size of the first region is smaller than a size of the first substrate layer.

6. The light detecting device according to claim 5 , wherein a size of the second region is smaller than the size of the first substrate layer.

7. The light detecting device according to claim 3 , wherein the first and second regions are separated by a separation region.

8. The light detecting device according to claim 3 , further comprising a third section, wherein the third section includes a memory portion configured to store signal-processed pixel data.

9. The light detecting device according to claim 3 , wherein the first logic portion outputs the first pixel data outside of the first region.

10. The light detecting device according to claim 3 , wherein the second logic portion outputs the second pixel data outside of the second region.

11. The light detecting device according to claim 3 , wherein pixel signals generated from a first side of the photoelectric conversion region are provided to the first logic portion and pixel signals generated from a second side of the photoelectric conversion region are provided to the second logic portion.

12. The light detecting device according to claim 3 , wherein the first logic portion outputs the first pixel data to the second logic portion or the second logic portion outputs the second pixel data to the first logic portion.

13. The light detecting device according to claim 12 , wherein the second logic portion outputs the first pixel data and the second pixel data outside the second region or the first logic portion outputs the first pixel data and the second pixel data outside the first region.

14. The light detecting device according to claim 3 , wherein the first section is stacked above the second section.

15. The light detecting device according to claim 8 , wherein the second wiring layer is connected to a wiring provided above the first, second and third sections.

16. A light detecting device, comprising:

a first substrate including:

a first substrate layer at a light incident side, the first substrate layer including a plurality of photodiodes; and

a first wiring layer at a side opposite the light incident side;

a second substrate including a second wiring layer and a second substrate layer,

wherein the first substrate and the second substrate are bonded together such that the first wiring layer and the second wiring layer are facing each other; and

a third substrate including a third wiring layer and a third substrate layer,

wherein the first substrate and the third substrate are bonded together such that the first wiring layer and the third wiring layer are facing each other,

wherein the first wiring layer and the second wiring layer are electrically connected to one another and the first wiring layer and the third wiring layer are electrically connected to one another,

wherein a size of the second substrate and a size of the third substrate are each smaller than a size of the first substrate, and

wherein the second wiring layer is connected to the first wiring layer through a first wire extending through the first substrate to the second substrate and provided above the first and second substrates and the third wiring layer is connected to the first wiring layer through a second wire extending through the first substrate to the third substrate and provided above the first and third substrates.

17. The light detecting device according to claim 16 , wherein the first wiring layer and the second wiring layer are electrically connected by a via.

18. The light detecting device according to claim 16 , further comprising a spacing region provided between the second substrate and the third substrate.

19. The light detecting device according to claim 16 , wherein the second substrate includes a first signal processing circuit and the third substrate includes a second signal processing circuit.

20. The light detecting device according to claim 19 , wherein a signal from the first signal processing circuit is conveyed to the second signal processing circuit and a result of a signal processing on the signal from the second signal processing circuit is output as an image signal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 8, 2020
From: IZUHARA, KUNIHIKO
To: SONY CORPORATION
Reel/Frame 053729/0678 →
Priority Claims (2)
JP 2014-087603 · Apr 21, 2014 · national
JP 2014-129952 · Jun 25, 2014 · national
Continuity (3)
Continuation 16284716 · Feb 25, 2019
Continuation 15302705
Related Publication 20200403020A1 · Dec 24, 2020