Universal network-attached memory architecture
Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes a common substrate and a first integrated circuit (IC) chiplet disposed on the common substrate. The first IC chiplet includes at least one processing element. A communications fabric switchably couples to the at least one processing element. A peripheral gearbox chiplet (PGC) includes a first port having a second memory-agnostic interface coupled to the first memory-agnostic interface of the first IC chiplet. The PGC includes a second port having a memory interface of a first type and interface conversion circuitry disposed between the second memory-agnostic interface and the memory interface of the first type.
1. A chiplet-based multi-chip module (MCM), comprising:
a package substrate;
a first integrated circuit (IC) chiplet disposed on the package substrate and comprising:
at least one processing element;
a communications fabric switchably coupled to the at least one processing element; and
a first memory-agnostic interface to transfer memory requests from the at least one processing element via the communications fabric;
a peripheral gearbox chiplet comprising:
a first port comprising a second memory-agnostic interface coupled to the first memory-agnostic interface of the first IC chiplet;
a second port comprising a memory interface of a first memory type; and
interface conversion circuitry disposed between the second memory-agnostic interface and the memory interface of the first memory type, the interface conversion circuitry comprising a memory controller of the first memory type.
2. The chiplet-based MCM of claim 1 , wherein:
the communications fabric comprises a network-on-chip (NoC) circuit.
3. The chiplet-based MCM of claim 2 , wherein:
the first memory-agnostic interface comprises a NoC media access controller (MAC).
4. The chiplet-based MCM of claim 3 , wherein:
the first memory-agnostic interface further comprises a first memory-agnostic die-to-die interface that cooperates with the NOC MAC.
5. The chiplet-based MCM of claim 4 , wherein:
the first memory-agnostic die-to-die interface comprises a universal chiplet interconnect express (UCIe) or Universal Memory Interface (UMI) interface.
6. The chiplet-based MCM of claim 1 , further comprising:
a memory chiplet of the first memory type coupled to the second port of the peripheral gearbox chiplet and disposed on the package substrate.
7. The chiplet-based MCM of claim 6 , wherein:
the memory chiplet of the first memory type is coupled to the second port of the peripheral gearbox chiplet in a 2.5D packaging configuration.
8. The chiplet-based MCM of claim 6 , wherein:
the memory chiplet of the first memory type is coupled to the second port of the peripheral gearbox chiplet in a 3.0D packaging configuration.
9. The chiplet-based MCM of claim 8 , wherein:
the memory interface of the first memory type comprises a high-bandwidth memory (HBM) memory interface; and
the memory chiplet comprises an HBM chiplet.
10. The chiplet-based MCM of claim 1 , wherein:
the memory interface of the first memory type comprises one of a double-data rate (DDR) memory interface, low-power double data rate (LPDDR) memory interface, a graphics double data rate (GDDR) memory interface or a compute express link (CXL) memory interface.
11. An integrated circuit (IC) chiplet apparatus, comprising:
a peripheral gearbox chiplet comprising:
a first port comprising a first memory-agnostic interface to communicate memory-related information with a second memory-agnostic interface of a first IC chiplet, the first memory-agnostic interface comprising
a network-on-chip (NoC) media access controller (MAC) to communicate with a communications fabric of the first IC chiplet, and
a first memory-agnostic die-to-die interface that cooperates with the NOC MAC;
a second port comprising a memory interface of a first memory type; and
interface conversion circuitry disposed between the first memory-agnostic interface of the first port and the memory interface of the first memory type, the interface conversion circuitry comprising a memory controller of the first memory type.
12. The IC chiplet apparatus of claim 11 , wherein:
the first memory-agnostic interface exhibits a first lateral dimension; and
wherein the memory interface of the first memory type exhibits a second lateral dimension that is larger than the first lateral dimension.
13. The IC chiplet apparatus of claim 12 , wherein:
the first memory-agnostic die-to-die interface comprises a universal chiplet interconnect express (UCIe) or Universal Memory Interface (UMI) interface.
14. The IC chiplet apparatus of claim 11 , further comprising:
a memory chiplet of the first memory type coupled to the second port of the peripheral gearbox chiplet.
15. The IC chiplet apparatus of claim 14 , wherein:
the memory chiplet of the first memory type comprises a high bandwidth memory (HBM) chiplet.
16. The IC chiplet apparatus of claim 15 , wherein:
the memory chiplet of the first memory type is coupled to the second port of the peripheral gearbox chiplet in a 2.5D packaging configuration.
17. The IC chiplet apparatus of claim 15 , wherein:
the memory chiplet of the first memory type is coupled to the second port of the peripheral gearbox chiplet in a 3.0D packaging configuration.
18. A chiplet-based multi-chip module (MCM), comprising:
a package substrate;
a first integrated circuit (IC) chiplet disposed on the package substrate and comprising:
at least one processing element;
a communications fabric switchably coupled to the at least one processing element;
a first memory-agnostic interface to transfer first memory requests from the at least one processing element via the communications fabric; and
a second memory-agnostic interface to transfer second memory requests from the at least one processing element via the communications fabric;
a first peripheral gearbox chiplet comprising:
a first port comprising a second memory-agnostic interface coupled to the first memory-agnostic interface of the first IC chiplet;
a second port comprising a first memory interface;
first interface conversion circuitry disposed between the second memory-agnostic interface and the first memory interface; and
a second peripheral gearbox chiplet comprising:
a third port comprising a third memory-agnostic interface coupled to the second memory-agnostic interface of the first IC chiplet;
a fourth port comprising a second memory interface; and
second interface conversion circuitry disposed between the third memory-agnostic interface and the second memory interface.
19. The chiplet-based MCM of claim 18 , wherein:
the first memory interface comprises a high bandwidth memory (HBM) interface; and
the second memory interface comprises one of a double-data rate (DDR) memory interface, a low-power double data rate (LPDDR) memory interface, a graphics double data rate (GDDR) memory interface or a compute express link (CXL) memory interface.
20. The chiplet-based MCM of claim 18 , wherein:
the communications fabric comprises a network-on-chip (NoC) circuit.
21. The chiplet-based MCM of claim 18 , wherein:
the first memory-agnostic interface and the second memory-agnostic interface collectively occupy a beachfront length portion associated with the first IC chiplet; and
wherein the second port comprising the first memory interface and the fourth port comprising the second memory interface collectively occupy a length that is larger than the beachfront length portion.
22. The chiplet-based MCM of claim 18 , wherein:
the first memory interface is of a first type; and
the second memory interface is of a second type that is different than the first type.