Systems and methods of programming for in-memory processing
Provided are systems, methods, and apparatuses for systems and methods of programming processes in processing in memory (PIM) systems. In one or more examples, the systems, devices, and methods include enabling, via a processor, a PIM manager for processing of PIM instructions, the PIM manager being located on a base die of a stacked memory module; enabling, via the PIM manager, a plurality of processing units of one or more memory dies of the stacked memory module for processing; compiling source code comprising the PIM instructions into machine code; loading, via PIM manager, the machine code into an allocation of memory of the stacked memory module; and executing, via the plurality of processing units, the PIM instructions based on loading the machine code into the memory of the stacked memory module.
1 . A method of programming processing-in-memory (PIM) processes, the method comprising:
enabling, via a processor, a PIM manager for processing of PIM instructions, the PIM manager being located on a base die of a stacked memory module;
enabling, via the PIM manager, a plurality of processing units of one or more memory dies of the stacked memory module for processing;
compiling, via a compiler of the PIM manager, source code comprising the PIM instructions into machine code, the machine code being stored in a memory of a host of the stacked memory module;
loading, via the compiler and a driver of the PIM manager, the machine code into an allocation of memory of the stacked memory module; and
executing, via the plurality of processing units, the PIM instructions based on loading the machine code into the memory of the stacked memory module.
2 . The method of claim 1 , wherein a first portion of the allocation of memory comprises a first portion of the machine code, the first portion of the machine code comprising:
a first dataset used by the plurality of processing units of the one or more memory dies in executing at least a first portion of the PIM instructions, and
a second dataset used by processing units on the base die in executing at least a second portion of the PIM instructions.
3 . The method of claim 1 , wherein a second portion of the allocation of memory comprises a second portion of the machine code, the second portion of the machine code comprising:
a first portion of the PIM instructions used by the plurality of processing units of the one or more memory dies in executing the first portion of the PIM instructions, and
a second portion of the PIM instructions used by processing units on the base die.
4 . The method of claim 3 , wherein:
a third portion of the allocation of memory comprises a third portion of the machine code, the third portion of the machine code comprising one or more load store instructions managed by the PIM manager, and
the PIM manager issues an instruction from the one or more load store instructions to trigger execution of the first portion of the PIM instructions.
5 . The method of claim 1 , wherein the PIM manager comprises a base die processor configured to direct processing on the plurality of processing units of one or more memory dies and to orchestrate, via a shared buffer of the PIM manager, data movement between the plurality of processing units of the one or more memory dies and processing units on the base die.
6 . The method of claim 1 , wherein:
the PIM manager is enabled for processing based on the processor writing an activation value to an enable register included in the allocation of memory, and
the PIM manager enables the plurality of processing units for processing based on the PIM manager being enabled.
7 . The method of claim 1 , further comprising:
determining execution of the PIM instructions is complete based on polling a done register included in the allocation of memory and determining a completion value of the done register indicates execution of the PIM instructions is complete,
wherein the PIM manager writes the completion value to the done register based on the PIM manager determining a plurality of registers respectively associated with the plurality of processing units indicate that execution of the PIM instructions by the plurality of processing units is complete.
8 . The method of claim 1 , further comprising writing a deactivation value to a stop register included in the allocation of memory to deactivate the PIM manager, wherein deactivating the PIM manager triggers the PIM manager to deactivate the plurality of processing units.
9 . The method of claim 1 , further comprising writing an exception value to an exception register included in the allocation of memory to trigger an exception based on execution of the PIM instructions.
10 . The method of claim 1 , wherein the one or more memory dies comprise one or more layers of memory dies stacked on top of the base die.
11 . The method of claim 1 , wherein:
the processor comprises at least one of a graphical processing unit (GPU) communicatively coupled to the PIM manager or a central processing unit (CPU) of the host of the stacked memory module that is communicatively coupled to the PIM manager, and
the PIM manager comprises a processor and memory for PIM management.
12 . A device comprising:
one or more processors; and
memory storing instructions that, when executed by the one or more processors, cause the device to:
enable a PIM manager for processing of PIM instructions, the PIM manager being located on a base die of a stacked memory module;
enable, via the PIM manager, a plurality of processing units of one or more memory dies of the stacked memory module for processing;
compile, via a compiler of the PIM manager, source code comprising the PIM instructions into machine code, the machine code being stored in a memory of a host of the stacked memory module;
load, via the compiler and a driver of the PIM manager, the machine code into an allocation of memory of the stacked memory module; and
execute, via the plurality of processing units, the PIM instructions based on loading the machine code into the memory of the stacked memory module.
13 . The device of claim 12 , wherein a first portion of the allocation of memory comprises a first portion of the machine code, the first portion of the machine code comprising:
a first dataset used by the plurality of processing units of the one or more memory dies in executing at least a first portion of the PIM instructions, and
a second dataset used by processing units on the base die in executing at least a second portion of the PIM instructions.
14 . The device of claim 12 , wherein a second portion of the allocation of memory comprises a second portion of the machine code, the second portion of the machine code comprising:
a first portion of the PIM instructions used by the plurality of processing units of the one or more memory dies in executing the first portion of the PIM instructions, and
a second portion of the PIM instructions used by processing units on the base die.
15 . The device of claim 14 , wherein:
a third portion of the allocation of memory comprises a third portion of the machine code, the third portion of the machine code comprising one or more load store instructions managed by the PIM manager, and
the PIM manager issues an instruction from the one or more load store instructions to trigger execution of the first portion of the PIM instructions.
16 . The device of claim 12 , wherein the PIM manager is configured to orchestrate, via a shared buffer of the PIM manager, data movement between the plurality of processing units of the one or more memory dies and processing units on the base die.
17 . The device of claim 12 , wherein:
the instructions, when executed by the one or more processors, further cause the device to determine execution of the PIM instructions is complete based on polling a done register included in the allocation of memory and determining a completion value of the done register indicates execution of the PIM instructions is complete, and
the PIM manager writes the completion value to the done register based on the PIM manager determining a plurality of registers respectively associated with the plurality of processing units indicate that execution of the PIM instructions by the plurality of processing units is complete.
18 . A non-transitory computer-readable medium storing code that comprises instructions executable by a processor to:
enable a PIM manager for processing of PIM instructions, the PIM manager being located on a base die of a stacked memory module;
enable, via the PIM manager, a plurality of processing units of one or more memory dies of the stacked memory module for processing;
compile, via a compiler of the PIM manager, source code comprising the PIM instructions into machine code, the machine code being stored in a memory of a host of the stacked memory module;
load, via the compiler and a driver of the PIM manager, the machine code into an allocation of memory of the stacked memory module; and
execute, via the plurality of processing units, the PIM instructions based on loading the machine code into the memory of the stacked memory module.
19 . The non-transitory computer-readable medium of claim 18 , wherein a first portion of the allocation of memory comprises a first portion of the machine code, the first portion of the machine code comprising:
a first dataset used by the plurality of processing units of the one or more memory dies in executing at least a first portion of the PIM instructions, and
a second dataset used by processing units on the base die in executing at least a second portion of the PIM instructions.
20 . The non-transitory computer-readable medium of claim 18 , wherein a second portion of the allocation of memory comprises a second portion of the machine code, the second portion of the machine code comprising:
a first portion of the PIM instructions used by the plurality of processing units of the one or more memory dies in executing the first portion of the PIM instructions, and
a second portion of the PIM instructions used by processing units on the base die.