IP Library › Granted Patent US 12,075,713
Granted Patent B2
US 12,075,713 · App. 18/321,843 · Granted Aug 27, 2024

Phase-change memory and method of forming same

Inventor: Jau-Yi Wu (Zhubei, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H10N70/826H10B63/30H10N70/021H10N70/231H10N70/841
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Quick Facts
Patent No.
US 12,075,713
App. No.
18/321,843
Granted
Aug 27, 2024
Kind
B2
Abstract

A device and a method of forming the same are provided. The device includes a substrate, a first dielectric layer over the substrate, a bottom electrode extending through the first dielectric layer, a first buffer layer over the bottom electrode, a phase-change layer over the first buffer layer, a top electrode over the phase-change layer, and a second dielectric layer over the first dielectric layer. The second dielectric layer surrounds the phase-change layer and the top electrode. A width of the top electrode is greater than a width of the bottom electrode.

Claims (45)

1. A device comprising:

a first dielectric layer;

a conductive line in the first dielectric layer;

a second dielectric layer over the conductive line and the first dielectric layer;

a bottom electrode within the second dielectric layer, the bottom electrode being electrically connected to the conductive line, the bottom electrode having a first width;

a first buffer layer over the bottom electrode, the first buffer layer having a second width;

a phase-change layer over the first buffer layer, the phase-change layer having a third width greater than the first width, the first buffer layer separating the phase-change layer from the bottom electrode;

a top electrode over the phase-change layer; and

a third dielectric layer over the second dielectric layer, the third dielectric layer extending along sidewalls of the phase-change layer.

2. The device of claim 1 , wherein the second width is less than the third width.

3. The device of claim 1 , wherein the second width is greater than the first width.

4. The device of claim 1 , further comprising a second buffer layer between the phase-change layer and the top electrode.

5. The device of claim 4 , wherein the first buffer layer and the second buffer layer comprise a same material.

6. The device of claim 4 , wherein the first buffer layer and the second buffer layer comprise different materials.

7. The device of claim 4 , wherein the second buffer layer has a fourth width greater than the second width.

8. A device comprising:

a substrate;

a first interconnect structure over the substrate;

a first dielectric layer over the first interconnect structure;

a bottom electrode embedded in the first dielectric layer;

a phase-change layer over the bottom electrode, wherein a width of the phase-change layer is greater than a width of the bottom electrode;

a first buffer layer over the phase-change layer;

a second buffer layer between the bottom electrode and the phase-change layer, wherein an upper surface of the second buffer layer is level with an upper surface of the first dielectric layer;

a top electrode over the first buffer layer; and

a second dielectric layer over the first dielectric layer, wherein the second dielectric layer is in physical contact with sidewalls of the phase-change layer and sidewalls of the top electrode.

9. The device of claim 8 , wherein the first dielectric layer extends along sidewalls of the second buffer layer.

10. The device of claim 8 , wherein the first buffer layer comprises amorphous carbon.

11. The device of claim 10 , wherein the first buffer layer comprises amorphous carbon, and wherein the second buffer layer comprises amorphous carbon.

12. The device of claim 8 , wherein the second buffer layer comprises amorphous carbon.

13. The device of claim 8 , wherein the first buffer layer has a width in a range between 5 nm and 40 nm.

14. The device of claim 8 , wherein the second buffer layer has a thickness in a range between 1 nm and 10 nm.

15. A device comprising:

a substrate;

a first dielectric layer over the substrate;

a bottom electrode extending through the first dielectric layer;

a first buffer layer over the bottom electrode;

a phase-change layer over the first buffer layer;

a second buffer layer over the phase-change layer, wherein the second buffer layer and the first buffer layer have different widths;

a top electrode over the second buffer layer, wherein a width of the top electrode is greater than a width of the bottom electrode; and

a second dielectric layer over the first dielectric layer, the second dielectric layer surrounding the phase-change layer and the top electrode.

16. The device of claim 15 , wherein at least one of the first buffer layer and the second buffer layer comprises amorphous carbon.

17. The device of claim 15 , wherein a topmost surface of the first buffer layer is substantially level with a top surface of the first dielectric layer.

18. The device of claim 15 , wherein each of the first buffer layer and the second buffer layer comprises amorphous carbon.

19. The device of claim 15 , wherein the first buffer layer has a thickness in a range between 1 nm and 10 nm.

20. The device of claim 15 , wherein the first buffer layer has a width in a range between 5 nm and 40 nm.

Continuity (3)
Continuation 17666230 · Feb 7, 2022
Division 16727363 · Dec 26, 2019
Related Publication 20230320239A1 · Oct 5, 2023
Cited By (1)
US 12,477,961