IP Library › Granted Patent US 12,095,555
Granted Patent B2
US 12,095,555 · App. 18/492,140 · Granted Sep 17, 2024

Method and apparatus for channel encoding/decoding in a communication or broadcasting system

Inventors: Kyung-Joong Kim (Seoul, KR); Seho Myung (Seoul, KR); Min Jang (Seongnam-si, KR); Hong-Sil Jeong (Suwon-si, KR); Jae-Yoel Kim (Seongnam-si, KR); Seok-Ki Ahn (Suwon-si, KR)
Assignee: Samsung Electronics Co., Ltd.
H04L1/0041H03M13/00H03M13/05H03M13/1102H03M13/116H03M13/1165H03M13/1177H03M13/25H03M13/256H03M13/616H03M13/6393H03M13/6513H04L1/00
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Quick Facts
Patent No.
US 12,095,555
App. No.
18/492,140
Granted
Sep 17, 2024
Kind
B2
Abstract

A channel encoding method in a communication or broadcasting system is provided. The channel encoding method includes reading a first sequence corresponding to a parity check matrix, converting the first sequence to a second sequence by applying a certain rule to a block size corresponding to a parity check matrix and the first sequence, and encoding information bits based on the second sequence. The block size has at least two different integer values.

Claims (113)

1. A method for encoding in a communication or broadcasting system supporting a low density parity check (LDPC) code, the method comprising:

identifying a block size Z;

identifying a parity check matrix, based on the block size Z;

generating codeword, based on input bits and the parity check matrix, wherein the codeword includes parity bits and a first part of the input bits; and

generating coded bits for transmission based on a circular buffer-based rate matching (CBRM) and the codeword;

wherein a second part of the input bits is not included in the codeword.

2. The method of claim 1 , wherein the generating of the coded bits for transmission comprises:

performing the circular buffer-based rate matching on the codeword to identify the coded bits for transmission.

3. The method of claim 1 ,

wherein the generating of the codeword comprises puncturing of the second part of the input bits; and

wherein the input bits includes the first part and the second part.

4. The method of claim 1 , wherein the second part of the input bits includes at least one information bit corresponding to a first column block of the parity check matrix.

5. The method of claim 1 ,

wherein the generating of the coded bits for transmission based on the CBRM and the codeword comprising identifying an index k 0 ; and

wherein the index k 0 indicates a bit of the codeword corresponding to a start position of the coded bits for transmission.

6. The method of claim 5 ,

wherein the index k 0 is identified based on rv idx , N cb , and the block size Z,

wherein the rv idx is a number for a redundancy version, and

wherein the N cb is a length of a buffer.

7. The method of claim 6 ,

wherein the rv idx is an integer corresponding to one of 0, 1, 2, or 3, and

wherein the N cb is equal to or less than a number of the codeword.

8. The method of claim 1 , further comprising:

identifying a size related to information bits to encode,

wherein the block size Z is identified based on the size related to the information bits.

9. The method of claim 1 , wherein the parity check matrix includes Z×Z zero matrices and Z×Z circular permutation matrices.

10. An encoder in a communication or broadcasting system supporting a low density parity check (LDPC) code, the encoder comprising:

a transceiver; and

at least one processor coupled to the transceiver and configured to:

identify a block size Z,

identify a parity check matrix, based on the block size Z; and

generate codeword, based on input bits and the parity check matrix,

wherein the codeword includes parity bits and a first part of the input bits, and

generate coded bits for transmission, based on a circular buffer-based rate matching (CBRM) and the codeword,

wherein a second part of the input bits is not included in the codeword.

11. The encoder of claim 10 , wherein the at least one processor is further configured to:

perform the circular buffer-based rate matching on the codeword to identify the coded bits for transmission.

12. The encoder of claim 10 ,

wherein the at least one processor is further configured to puncture of the second part of the input bits, and

wherein the input bits includes the first part and the second part.

13. The encoder of claim 10 , wherein the second part of the input bits includes at least one information bit corresponding to a first column block of the parity check matrix.

14. The encoder of claim 10 ,

wherein the at least one processor is further configured to identify an index k 0 , and

wherein the index k 0 indicates a bit of the codeword corresponding to a start position of the coded bits for transmission.

15. The encoder of claim 14 ,

wherein the index k 0 is identified based on rv idx , N cb , and the block size Z,

wherein the rv idx is a number for a redundancy version, and

wherein the N cb is a length of a buffer.

16. The encoder of claim 15 ,

wherein the rv idx is an integer corresponding to one of 0, 1, 2, or 3, and

wherein the N cb is equal to or less than a number of the codeword.

17. The encoder of claim 10 ,

wherein the at least one processor is further configured to identify a size related to information bits to encode, and

wherein the block size Z is identified based on the size related to the information bits.

18. The encoder of claim 10 , wherein the parity check matrix includes Z×Z zero matrices and Z×Z circular permutation matrices.

19. A method for decoding in a communication or broadcasting system supporting a low density parity check (LDPC) code, the method comprising:

receiving, from a transmitter, a signal corresponding to coded bits for transmission;

demodulating the signal to generate values for LDPC decoding; and

identifying input bits by decoding based on a parity check matrix and the values for LDPC decoding,

wherein the coded bits for transmission are generated based on a circular buffer-based rate matching (CBRM) and codeword,

wherein the codeword are generated, based on the input bits and the parity check matrix,

wherein the codeword includes parity bits and a first part of the input bits,

wherein the parity check matrix is identified based on a block size Z, and

wherein a second part of the input bits is not included in the codeword.

20. The method of claim 19 , wherein the circular buffer-based rate matching is performed on the codeword to identify the coded bits for transmission.

21. The method of claim 19 ,

wherein the second part is punctured in the input bits, and

wherein the input bits includes the first part and the second part.

22. The method of claim 19 , wherein the second part of the input bits includes at least one information bit corresponding to a first column block of the parity check matrix.

23. The method of claim 19 ,

wherein the coded bits for transmission is generated based on the CBRM, the codeword and an index k 0 , and

wherein the index k 0 indicates a bit of the codeword corresponding to a start position of the coded bits for transmission.

24. The method of claim 23 ,

wherein the index k 0 is identified based on rv idx , N cb , and the block size Z,

wherein the rv idx is a number for a redundancy version, and

wherein the N cb is a length of a buffer.

25. The method of claim 24 ,

wherein the rv idx is an integer corresponding to one of 0, 1, 2, or 3, and

wherein the N cb is equal to or less than a number of the codeword.

26. The method of claim 19 , wherein the block size Z is identified based on a size related to information bits.

27. The method of claim 19 , wherein the parity check matrix includes Z×Z zero matrices and Z×Z circular permutation matrices.

28. The method of claim 19 , wherein the identifying of the input bits by decoding based on the parity check matrix and the values for LDPC decoding comprises:

decoding based on the parity check matrix, the values for LDPC decoding, and predetermined-valued set for the second part of the input bits.

29. A decoder in a communication or broadcasting system supporting a low density parity check (LDPC) code, the decoder comprising:

a transceiver; and

at least one processor coupled to the transceiver and configured to:

control the transceiver to receive a signal corresponding to coded bits for transmission from a transmitter,

demodulate the signal to generate values for LDPC decoding, and

identify input bits by decoding based on a parity check matrix and the values for LDPC decoding,

wherein the coded bits for transmission is generated based on a circular buffer-based rate matching (CBRM) and codeword,

wherein the codeword is generated, based on the input bits and the parity check matrix,

wherein the codeword includes parity bits and a first part of the input bits,

wherein the parity check matrix, is identified based on a block size Z, and

wherein a second part of the input bits is not included in the codeword.

30. The decoder of claim 29 , wherein the circular buffer-based rate matching is performed on the codeword to identify the coded bits for transmission.

31. The decoder of claim 29 ,

wherein the second part is punctured in the input bits, and

wherein the input bits includes the first part and the second part.

32. The decoder of claim 29 , wherein the second part of the input bits includes at least one information bit corresponding to a first column block of the parity check matrix.

33. The decoder of claim 29 ,

wherein the coded bits for transmission is generated based on the CBRM, the codeword and an index k 0 , and

wherein the index k 0 indicates a bit of the codeword corresponding to a start position of the coded bits for transmission.

34. The decoder of claim 33 ,

wherein the index k 0 is identified based on rv idx , N cb , and the block size Z, and

wherein the rv idx is a number for a redundancy version, and

wherein the N cb is a length of a buffer.

35. The decoder of claim 34 ,

wherein the rv idx is an integer corresponding to one of 0, 1, 2, or 3, and

wherein the N cb is equal to or less than a number of the codeword.

36. The decoder of claim 29 , wherein the block size Z is identified based on a size related to information bits.

37. The decoder of claim 29 , wherein the parity check matrix includes Z×Z zero matrices and Z×Z circular permutation matrices.

38. The decoder of claim 29 ,

wherein identifying the input bits by decoding based on the parity check matrix and the values for LDPC decoding comprises decoding based on the parity check matrix, the values for LDPC decoding, and predetermined-valued set for the second part of the input bits.

Priority Claims (5)
KR 10-2015-0165114 · Nov 24, 2015 · national
KR 10-2016-0002929 · Jan 8, 2016 · national
KR 10-2016-0102635 · Aug 11, 2016 · national
KR 10-2016-0105807 · Aug 19, 2016 · national
KR 10-2016-0149882 · Nov 10, 2016 · national
Continuity (6)
Continuation 18156867 · Jan 19, 2023
Continuation 17564531 · Dec 29, 2021
Continuation 17109476 · Dec 2, 2020
Continuation 16730412 · Dec 30, 2019
Continuation 15361283 · Nov 25, 2016
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