IP Library Granted Patent US 12,100,721
Granted Patent B2
US 12,100,721 · App. 18/224,691 · Granted Sep 24, 2024

Solid-state image pickup device and electronic apparatus having a divided pixel separation wall

Inventors: Atsushi Masagaki (Kanagawa, JP); Yusuke Tanaka (Kanagawa, JP)
Assignee: SONY GROUP CORPORATION
H01L27/14621G02B7/34H01L21/76H01L27/14605H01L27/14607H01L27/14627H01L27/1463H01L27/14641H01L27/14612H01L27/1464H04N25/62H04N25/76H04N25/778
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Quick Facts
Patent No.
US 12,100,721
App. No.
18/224,691
Granted
Sep 24, 2024
Kind
B2
Abstract

The present disclosure relates to a solid-state image pickup device and an electronic apparatus that are capable of preventing leakage of charges between adjacent pixels. A plurality of pixels perform photoelectric conversion on light incident from a back surface via different on-chip lenses for each pixel. A pixel separation wall is formed between pixels adjacent to each other, and includes a front-side trench formed from a front surface and a backside trench formed from the back surface. A wiring layer is provided on the front surface. The present disclosure is applicable to, for example, a backside illuminated CMOS image sensor.

Claims (50)

1. A light detecting device, comprising:

a pixel, including:

a first photodiode, a second photodiode, a third photodiode, and a fourth photodiode disposed in a semiconductor substrate;

a divided pixel separation wall disposed in the semiconductor substrate,

wherein a first portion of the divided pixel separation wall is disposed between the first photodiode and the second photodiode,

wherein a second portion of the divided pixel separation wall is disposed between the second photodiode and the third photodiode,

wherein a third portion of the divided pixel separation wall is disposed between the third photodiode and the fourth photodiode,

wherein a fourth portion of the divided pixel separation wall is disposed between the first photodiode and the fourth photodiode;

a first impurity region disposed in the semiconductor substrate and between the first photodiode and the second photodiode;

a second impurity region disposed in the semiconductor substrate and between the second photodiode and the third photodiode;

a third impurity region disposed in the semiconductor substrate and between the third photodiode and the fourth photodiode; and

a fourth impurity region disposed in the semiconductor substrate and between the first photodiode and the fourth photodiode.

2. The light detecting device of claim 1 , wherein a length of the first portion of the divided pixel separation wall is different than a length of the second portion of the divided pixel separation wall.

3. The light detecting device of claim 2 , wherein the length of the first portion of the divided pixel separation wall is different than a length of the fourth portion of the divided pixel separation wall.

4. The light detecting device of claim 2 , wherein the length of the second portion of the divided pixel separation wall is greater than the length of the first portion of the divided pixel separation wall.

5. The light detecting device of claim 2 , wherein a length of the third portion of the divided pixel separation wall is greater than the length of the first portion of the divided pixel separation wall.

6. The light detecting device of claim 1 , wherein the first to fourth impurity regions are overflow paths.

7. The light detecting device of claim 1 , wherein an impurity concentration of the first impurity region is greater than an impurity concentration of the second impurity region.

8. The light detecting device of claim 7 , wherein an impurity concentration of the fourth impurity region is greater than an impurity concentration of the third impurity region.

9. The light detecting device of claim 1 , further comprising:

first, second, third, and fourth transfer transistors, wherein the first transfer transistor is coupled to the first photodiode, wherein the second transfer transistor is coupled to the second photodiode, wherein the third transfer transistor is coupled to the third photodiode, and wherein the fourth transfer transistor is coupled to the fourth photodiode.

10. The light detecting device of claim 9 , further comprising:

a floating diffusion region, wherein the first, second, third, and fourth transfer transistors are coupled to the floating diffusion region.

11. The light detecting device of claim 1 , further comprising:

an on-chip lens, wherein the first photodiode, the second photodiode, the third photodiode, and the fourth photodiode are configured to receive light through the on-chip lens.

12. A light detecting device, comprising,

a pixel, including:

a first photodiode, a second photodiode, a third photodiode, and a fourth photodiode disposed in a semiconductor substrate;

a divided pixel separation wall disposed in the semiconductor substrate,

wherein a first portion of the divided pixel separation wall is disposed between the first photodiode and the second photodiode,

wherein a second portion of the divided pixel separation wall is disposed between the second photodiode and the third photodiode,

wherein a third portion of the divided pixel separation wall is disposed between the third photodiode and the fourth photodiode,

wherein a fourth portion of the divided pixel separation wall is disposed between the first photodiode and the fourth photodiode;

a first overflow path disposed in the semiconductor substrate and between the first photodiode and the second photodiode;

a second overflow path disposed in the semiconductor substrate and between the second photodiode and the third photodiode;

a third overflow path disposed in the semiconductor substrate and between the third photodiode and the fourth photodiode, and

a fourth overflow path disposed in the semiconductor substrate and between the first photodiode and the fourth photodiode.

13. The light detecting device of claim 12 , wherein a length of the first portion of the divided pixel separation wall is different than a length of the second portion of the divided pixel separation wall.

14. The light detecting device of claim 13 , wherein the length of the first portion of the divided pixel separation wall is different than a length of the fourth portion of the divided pixel separation wall.

15. The light detecting device of claim 13 , wherein the length of the second portion of the divided pixel separation wall is greater than the length of the first portion of the divided pixel separation wall.

16. The light detecting device of claim 13 , wherein a length of the third portion of the divided pixel separation wall is greater than the length of the first portion of the divided pixel separation wall.

17. The light detecting device of claim 12 , wherein stored charges of one of the first photodiode or the fourth photodiode overflow to the other of the first photodiode or the fourth photodiode.

18. The light detecting device of claim 12 , wherein stored charges of one of the second photodiode or the third photodiode overflow to the other of the second photodiode or the third photodiode.

19. The light detecting device of claim 12 , wherein a first pixel signal based on stored charges of the first photodiode and stored charges of the fourth photodiode and a second pixel signal based on stored charges of the second photodiode and stored charges of the third photodiode are used for phase difference detection.

20. The light detecting device of claim 12 , further comprising:

first, second, third, and fourth transfer transistors, wherein the first transfer transistor is coupled to the first photodiode, wherein the second transfer transistor is coupled to the second photodiode, wherein the third transfer transistor is coupled to the third photodiode, and wherein the fourth transfer transistor is coupled to the fourth photodiode.

21. The light detecting device of claim 20 , further comprising:

a floating diffusion region, wherein the first, second, third, and fourth transfer transistors are coupled to the floating diffusion region.

22. The light detecting device of claim 12 , further comprising:

an on-chip lens, wherein the first photodiode, the second photodiode, the third photodiode, and the fourth photodiode are configured to receive light through the on-chip lens.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 16, 2024
From: MASAGAKI, ATSUSHI; TANAKA, YUSUKE
To: SONY CORPORATION
Reel/Frame 066335/0952 →
CHANGE OF NAME Recorded Jan 16, 2024
From: SONY CORPORATION
To: SONY GROUP CORPORATION
Reel/Frame 066336/0015 →
Priority Claims (1)
JP 2016-013613 · Jan 27, 2016 · national
Continuity (6)
Continuation 17863468 · Jul 13, 2022
Continuation 17307556 · May 4, 2021
Continuation 16849866 · Apr 15, 2020
Continuation 16539691 · Aug 13, 2019
Continuation 15559541
Related Publication 20230387154A1 · Nov 30, 2023