Integrated circuit structure

1. An integrated circuit (IC) structure comprising:

a substrate comprising a memory region and a logic region;

a first dielectric structure over the memory region;

a second dielectric structure laterally extending from the first dielectric structure to over the logic region, wherein the second dielectric structure has a thickness less than a thickness of the first dielectric structure;

a first via structure extending through the first dielectric structure, wherein a top segment of the first via structure is higher than a top surface of the first dielectric structure; and

a first memory cell structure over the first via structure.

2. The IC structure of claim 1 , wherein the first dielectric structure is a multilayer structure.

3. The IC structure of claim 1 , wherein the first dielectric structure comprises more than one dielectric material.

4. The IC structure of claim 1 , wherein the first dielectric structure comprises a first dielectric material, and the second dielectric structure comprises the first dielectric material.

5. The IC structure of claim 4 , wherein the first dielectric structure further comprises a second dielectric material different from the first dielectric material.

6. The IC structure of claim 1 , further comprising:

a first transistor in the memory region and electrically connected to the first via structure.

7. The IC structure of claim 6 , further comprising:

a second transistor in the logic region.

8. The IC structure of claim 1 , further comprising:

an interlayer dielectric (ILD) layer below the first dielectric structure and the second dielectric structure; and

a first conductive structure and a second conductive structure in the ILD layer, wherein the first conductive structure is in contact with the first via structure, the second conductive structure is over the logic region, and a top surface of the first conductive structure is substantially level with a top surface of the second conductive structure.

9. The IC structure of claim 8 , wherein the ILD layer has a first thickness in the memory region and a second thickness in the logic region, and a difference between the first and second thicknesses of the ILD layer is less than a difference between the thickness of the first dielectric structure and the thickness of the second dielectric structure.

10. The IC structure of claim 1 , further comprising:

a second via structure and a third via structure extending through the first dielectric structure, wherein the first, second, and third via structures are arranged substantially equidistantly.

11. The IC structure of claim 10 , further comprising:

a second memory cell structure over the second via structure; and

a third memory cell structure over the third via structure.

12. An IC structure comprising:

a memory region and a logic region;

a first dielectric structure in the memory region;

a second dielectric structure in the logic region, wherein the first dielectric structure has a top surface higher than a top surface of the second dielectric structure, wherein the second dielectric structure laterally extends from the first dielectric structure to over the logic region, wherein the second dielectric structure has a thickness less than a thickness of the first dielectric structure;

a plurality of via structures extending through the first dielectric structure, wherein a top segment of one of the plurality of via structures is higher than the top surface of the first dielectric structure; and

a plurality of memory cell structures over the plurality of via structures, respectively.

13. The IC structure of claim 12 , wherein the first dielectric structure comprises more than one dielectric layer.

14. The IC structure of claim 12 , wherein the first dielectric structure comprises a dielectric material the same as a dielectric material of the second dielectric structure.

15. The IC structure of claim 12 , wherein the first dielectric structure has more layers than the second dielectric structure.

16. An IC structure comprising:

a substrate comprising a memory region and a non-memory region;

a first interlayer dielectric (ILD) layer over the substrate;

a plurality of first metal lines in the first ILD layer;

a second ILD layer over the first ILD layer;

a plurality of second metal lines in the second ILD layer;

a first dielectric structure and a second dielectric structure over the second ILD layer, wherein the first dielectric structure overlaps the memory region, the second dielectric structure overlaps the non-memory region, and the first dielectric structure is thicker than the second dielectric structure;

a via structure provided within the first dielectric structure and protruding from the first dielectric structure; and

a memory cell structure over the via structure.

17. The IC structure of claim 16 , wherein a top surface of the first dielectric structure is higher than a top surface of the second dielectric structure, and a bottom surface of the first dielectric structure is substantially level with a bottom surface of the second dielectric structure.

18. The IC structure of claim 16 , wherein the first dielectric structure has a plurality of dielectric layers.

19. The IC structure of claim 16 , wherein the first dielectric structure comprises a material same as a material of the second dielectric structure.

20. The IC structure of claim 12 , further comprising:

a plurality of magnetic tunnel junction (MTJ) structures over the plurality of via structures, respectively.