IP Library Granted Patent US 12,132,020
Granted Patent B2
US 12,132,020 · App. 18/539,143 · Granted Oct 29, 2024

Low temperature bonded structures

Inventors: Cyprian Emeka Uzoh (San Jose, CA); Jeremy Alfred Theil (Mountain View, CA); Rajesh Katkar (Milpitas, CA); Guilian Gao (San Jose, CA); Laura Wills Mirkarimi (Sunol, CA)
Assignee: Adeia Semiconductor Bonding Technologies Inc.
H01L24/08H01L24/80H01L2224/08057H01L2224/08147H01L2224/80895H01L2224/80896
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Quick Facts
Patent No.
US 12,132,020
App. No.
18/539,143
Granted
Oct 29, 2024
Kind
B2
Abstract

Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.

Claims (7)

1. A microelectronic assembly, comprising:

a first substrate having a first surface;

a second substrate having a second surface, the first surface of the first substrate intimately bonded to the second surface of the second substrate; and

a bonded conductive interconnect disposed at the first surface and the second surface, the bonded conductive interconnect comprising at least a first conductive material embedded into the first substrate, a second conductive material embedded into the second substrate, and an electrically conductive fill region disposed between the first conductive material and the second conductive material, wherein the fill region comprises a non-linear mass that includes a third conductive material, and wherein the third conductive material has a higher melting point than a melting point of the first conductive material or the second conductive material.

2. The microelectronic assembly of claim 1 , further comprising a forth conductive material disposed between the first conductive material and the fill region and/or a fifth conductive material disposed between the second conductive material and the fill region.

3. The microelectronic assembly of claim 1 , wherein the fill region includes a non-metal material.

4. The microelectronic assembly of claim 1 , wherein the fill region has a non-linear concentration of the third conductive material within a volume of the fill region.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 11, 2024
From: UZOH, CYPRIAN EMEKA; THEIL, JEREMY ALFRED; KATKAR, RAJESH; GAO, GUILIAN; MIRKARIMI, LAURA WILLS
To: INVENSAS BONDING TECHNOLOGIES, INC.
Reel/Frame 067685/0990 →
CHANGE OF NAME Recorded Jun 11, 2024
From: INVENSAS BONDING TECHNOLOGIES, INC.
To: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
Reel/Frame 067686/0721 →
Continuity (5)
Division 17559485 · Dec 22, 2021
Continuation 16655002 · Oct 16, 2019
Continuation In Part 16363894 · Mar 25, 2019
Provisional Application 62656264 · Apr 11, 2018
Related Publication 20240113059A1 · Apr 4, 2024
Cited By (4)
US 12,506,114 US 12,545,010 US 12,622,307 US 12,727,514