Semiconductor device including resistor element
A semiconductor device includes a first pad defined on one surface of a first chip; a second pad defined on one surface of a second chip which is stacked on the first chip, and bonded to the first pad; a first resistor element defined in the first chip, and coupled to the first pad; and a second resistor element defined in the second chip, and coupled to the second pad.
1. A semiconductor device comprising:
a first pad defined on one surface of a first chip, the first chip includes a memory cell array disposed in a cell region and a first peripheral circuit disposed in a peripheral region outside of the cell region;
a second pad defined on one surface of a second chip, which is stacked on the first chip in a first direction, and bonded to the first pad, the second chip includes a second peripheral circuit in the peripheral region;
a first vertical resistor pattern, defined in the first chip and coupled to the first pad, extending in the first direction;
a second vertical resistor pattern defined in the second chip and coupled to the second pad, extending in the first direction; and
a first gate resistor pattern disposed on a substrate of the first chip,
wherein the first vertical resistor pattern and the second vertical resistor pattern are disposed between the first peripheral circuit and the second peripheral circuit in the peripheral region, and
wherein at least a portion of the first vertical resistor pattern and at least a portion of the second vertical resistor pattern overlap each other in the first direction that is perpendicular to the one surface of the first chip and the one surface of the second chip.
2. The semiconductor device according to claim 1 , wherein the first gate resistor pattern overlaps with at least one of the first vertical resistor pattern and the second vertical resistor pattern in the first direction.
3. The semiconductor device according to claim 1 , further comprising:
a second gate resistor pattern disposed on a substrate of the second chip and coupled to the second vertical resistor pattern.
4. The semiconductor device according to claim 3 , wherein the second gate resistor pattern overlaps with at least one of the first vertical resistor pattern and the second vertical resistor pattern in the first direction.